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riscv: pmp: remove previous implementation

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Overall diffstat with the new PMP code in place:

 18 files changed, 866 insertions(+), 1372 deletions(-)

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-04-06 22:59:35 -04:00 committed by Carles Cufí
parent 2fece49a14
commit 554f24661f
5 changed files with 1 additions and 1329 deletions
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14
arch/riscv/core/pmp/CMakeLists.txt
View file

@ -1,14 +0,0 @@
#
# Copyright (c) 2020 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_RISCV_PMP core_pmp.c)
zephyr_library_include_directories(
.
../../include
)

39
arch/riscv/core/pmp/Kconfig
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@ -1,39 +0,0 @@
# Physical Memory Protection (PMP) configuration options
# Copyright (c) 2020 BayLibre, SAS
# SPDX-License-Identifier: Apache-2.0
config PMP_SLOT
int "Number of PMP slot"
default 8
help
Depend of the arch/board. Take care to don't put value higher
than the Hardware allow you.
config PMP_POWER_OF_TWO_ALIGNMENT
bool "Power of two alignment"
default n
select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
select GEN_PRIV_STACKS
help
This option will reduce the PMP slot number usage but increase
the memory consumption.
config PMP_STACK_GUARD
bool "Thread Stack Guard"
default n
help
Enable Thread Stack Guards via PMP
if PMP_STACK_GUARD
config PMP_STACK_GUARD_MIN_SIZE
int "Guard size"
default 16
help
Minimum size (and alignment when applicable) of an stack guard
region, which guards the stack of a thread. The width of the
guard is set to 16 bytes, to accommodate the riscv
granularity.
endif # PMP_STACK_GUARD

1137
arch/riscv/core/pmp/core_pmp.c
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File diff suppressed because it is too large Load diff

126
arch/riscv/include/core_pmp.h
View file

@ -1,126 +0,0 @@
/*
* Copyright (c) 2020 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef CORE_PMP_H_
#define CORE_PMP_H_
/* Configuration register flags (cfg_val)*/
#define PMP_R 0x01 /* Allow read */
#define PMP_W 0x02 /* Allow write */
#define PMP_X 0x04 /* Allow execute */
#define PMP_A 0x18 /* Address-matching mode field */
#define PMP_L 0x80 /* PMP entry is locked */
#define PMP_OFF 0x00 /* Null region */
#define PMP_TOR 0x08 /* Top of range */
#define PMP_NA4 0x10 /* Naturally aligned four-byte region */
#define PMP_NAPOT 0x18 /* Naturally aligned power-of-two region */
#define PMP_SHIFT_ADDR 2
#define PMP_TYPE_MASK 0x18
#define TO_PMP_ADDR(addr) ((addr) >> PMP_SHIFT_ADDR)
#define FROM_PMP_ADDR(addr) ((addr) << PMP_SHIFT_ADDR)
#define TO_NAPOT_RANGE(size) (((size) - 1) >> 1)
#define TO_PMP_NAPOT(addr, size) TO_PMP_ADDR(addr | \
TO_NAPOT_RANGE(size))
#ifdef CONFIG_PMP_STACK_GUARD
#define PMP_GUARD_ALIGN_AND_SIZE CONFIG_PMP_STACK_GUARD_MIN_SIZE
#else
#define PMP_GUARD_ALIGN_AND_SIZE 0
#endif /* CONFIG_PMP_STACK_GUARD */
#ifdef CONFIG_RISCV_PMP
/*
* @brief Reset to 0 all PMP setup registers
*/
void z_riscv_pmp_clear_config(void);
#endif /* CONFIG_RISCV_PMP */
#if defined(CONFIG_USERSPACE)
/*
* @brief Configure RISCV user thread access to the stack
*
* Determine and save allow access setup in thread structure.
*
* @param thread Thread info data pointer.
*/
void z_riscv_init_user_accesses(struct k_thread *thread);
/*
* @brief Apply RISCV user thread access to the stack
*
* Write user access setup saved in this thread structure.
*
* @param thread Thread info data pointer.
*/
void z_riscv_configure_user_allowed_stack(struct k_thread *thread);
/*
* @brief Add a new RISCV stack access
*
* Add a new memory permission area in the existing
* pmp setup of the thread.
*
* @param thread Thread info data pointer.
* @param addr Start address of the memory area.
* @param size Size of the memory area.
* @param flags Pemissions: PMP_R, PMP_W, PMP_X, PMP_L
*
* @retval 0 if successful
* @retval -EINVAL if invalid parameters supplied
* @retval -ENOSPC if no free PMP entry
*/
int z_riscv_pmp_add_dynamic(struct k_thread *thread,
ulong_t addr,
ulong_t size,
unsigned char flags);
#endif /* CONFIG_USERSPACE */
#ifdef CONFIG_PMP_STACK_GUARD
/*
* @brief Configure RISCV stack guard for interrupt stack
*
* Write PMP registers to prevent RWX access from all privilege mode.
*/
void z_riscv_configure_interrupt_stack_guard(void);
/*
* @brief Configure RISCV stack guard
*
* Determine and save stack guard setup in thread structure.
*
* @param thread Thread info data pointer.
*/
void z_riscv_init_stack_guard(struct k_thread *thread);
/*
* @brief Apply RISCV stack guard
*
* Write stack guard setup saved in this thread structure.
*
* @param thread Thread info data pointer.
*/
void z_riscv_configure_stack_guard(struct k_thread *thread);
#endif /* CONFIG_PMP_STACK_GUARD */
#if defined(CONFIG_PMP_STACK_GUARD) || defined(CONFIG_USERSPACE)
/*
* @brief Initialize thread PMP setup value to 0
*
* @param thread Thread info data pointer.
*/
void z_riscv_pmp_init_thread(struct k_thread *thread);
#endif /* CONFIG_PMP_STACK_GUARD || CONFIG_USERSPACE */
#endif /* CORE_PMP_H_ */

14
include/zephyr/arch/riscv/thread.h
View file

@ -94,6 +94,7 @@ typedef struct _callee_saved _callee_saved_t;
struct _thread_arch {
#ifdef CONFIG_USERSPACE
ulong_t priv_stack_start;
ulong_t u_mode_pmpaddr_regs[CONFIG_PMP_SLOT];
ulong_t u_mode_pmpcfg_regs[CONFIG_PMP_SLOT / sizeof(ulong_t)];
unsigned int u_mode_pmp_domain_offset;
@ -105,19 +106,6 @@ struct _thread_arch {
ulong_t m_mode_pmpaddr_regs[PMP_M_MODE_SLOTS];
ulong_t m_mode_pmpcfg_regs[PMP_M_MODE_SLOTS / sizeof(ulong_t)];
#endif
/* legacy stuff below */
#ifdef CONFIG_PMP_STACK_GUARD
ulong_t s_pmpcfg[PMP_CFG_CSR_NUM_FOR_STACK_GUARD];
ulong_t s_pmpaddr[PMP_REGION_NUM_FOR_STACK_GUARD];
#endif
#ifdef CONFIG_USERSPACE
ulong_t priv_stack_start;
ulong_t u_pmpcfg[RISCV_PMP_CFG_NUM];
ulong_t u_pmpaddr[CONFIG_PMP_SLOT];
#endif
};
typedef struct _thread_arch _thread_arch_t;