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dts: bindings: gd32-dma: add config cell property

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Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2022-12-08 18:40:26 +09:00 committed by Carles Cufí
parent ad055bd5fc
commit 59044c6d63
10 changed files with 159 additions and 25 deletions
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4
dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
View file

@ -472,7 +472,7 @@
<15 0>, <16 0>, <17 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
@ -483,7 +483,7 @@
<60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};

4
dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
View file

@ -411,7 +411,7 @@
<15 0>, <16 0>, <17 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
@ -422,7 +422,7 @@
<60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
};

2
dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
View file

@ -97,7 +97,7 @@
interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
clocks = <&cctl GD32_CLOCK_DMA>;
dma-channels = <7>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};

4
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
View file

@ -496,7 +496,7 @@
<15 0>, <16 0>, <17 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
@ -507,7 +507,7 @@
<60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
};

4
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
View file

@ -625,7 +625,7 @@
clocks = <&cctl GD32_CLOCK_DMA0>;
resets = <&rctl GD32_RESET_DMA0>;
dma-channels = <8>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
@ -637,7 +637,7 @@
clocks = <&cctl GD32_CLOCK_DMA1>;
resets = <&rctl GD32_RESET_DMA1>;
dma-channels = <8>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
};

17
dts/bindings/dma/gd,gd32-dma-base.yaml Normal file
View file

@ -0,0 +1,17 @@
# Copyright (c) 2022, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
# SPDX-License-Identifier: Apache-2.0
include: dma-controller.yaml
properties:
reg:
required: true
interrupts:
required: true
dma-channels:
required: true
clocks:
required: true

75
dts/bindings/dma/gd,gd32-dma.yaml
View file

@ -4,25 +4,72 @@
description: |
GD32 DMA controller
channel: Select channel for data transmitting
config: A 32bit mask specifying the DMA channel configuration
- bit 6-7: Direction (see dma.h)
- 0x0: MEMORY to MEMORY
- 0x1: MEMORY to PERIPH
- 0x2: PERIPH to MEMORY
- 0x3: reserved for PERIPH to PERIPH
- bit 9: Peripheral address increase
- 0x0: no address increment between transfers
- 0x1: increment address between transfers
- bit 10: Memory address increase
- 0x0: no address increase between transfers
- 0x1: increase address between transfers
- bit 11-12: Peripheral data width
- 0x0: 8 bits
- 0x1: 16 bits
- 0x2: 32 bits
- 0x3: reserved
- bit 13-14: Memory data width
- 0x0: 8 bits
- 0x1: 16 bits
- 0x2: 32 bits
- 0x3: reserved
- bit 15: Peripheral Increment Offset Size
- 0x0: offset size is linked to the peripheral bus width
- 0x1: offset size is fixed to 4 (32-bit alignment)
- bit 16-17: Priority
- 0x0: low
- 0x1: medium
- 0x2: high
- 0x3: very high
Example of devicetree configuration
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
dmas = <&dma0 3 0>, <&dma0 5 GD32_DMA_PRIORITY_HIGH>;
dma-names = "rx", "tx";
};
"spi0" uses dma0 for transmitting and receiving in the example.
Each is named "rx" and "tx".
The channel cell assigns channel 3 to receive and channel 5 to transmit.
The config cell can take various configs.
But the setting used depends on each driver implementation.
Set the priority for the transmitting channel as HIGH, LOW(the default) for receive channel.
compatible: "gd,gd32-dma"
include: [dma-controller.yaml, reset-device.yaml]
include: [ "gd,gd32-dma-base.yaml" ]
properties:
reg:
required: true
interrupts:
required: true
dma-channels:
required: true
clocks:
required: true
"#dma-cells":
const: 1
const: 2
dma-cells:
- channel
- config

4
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -392,7 +392,7 @@
<34 0>, <35 0>, <36 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
@ -403,7 +403,7 @@
<79 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>;
#dma-cells = <1>;
#dma-cells = <2>;
status = "disabled";
};
};

20
include/zephyr/drivers/dma/dma_gd32.h Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_
#define ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_
#define GD32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
#define GD32_DMA_CONFIG_PERIPH_ADDR_INC(config) ((config >> 9) & 0x1)
#define GD32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1)
#define GD32_DMA_CONFIG_PERIPH_WIDTH(config) ((config >> 11) & 0x3)
#define GD32_DMA_CONFIG_MEMORY_WIDTH(config) ((config >> 13) & 0x3)
#define GD32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1)
#define GD32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
#define GD32_DMA_FEATURES_FIFO_THRESHOLD(threshold) (threshold & 0x3)
#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_ */

50
include/zephyr/dt-bindings/dma/gd32_dma.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
/* macros for channel-cfg */
/* direction defined on bits 6-7 */
#define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
#define GD32_DMA_MEMORY_TO_MEMORY GD32_DMA_CH_CFG_DIRECTION(0)
#define GD32_DMA_MEMORY_TO_PERIPH GD32_DMA_CH_CFG_DIRECTION(1)
#define GD32_DMA_PERIPH_TO_MEMORY GD32_DMA_CH_CFG_DIRECTION(2)
/* periph increase defined on bit 9 as true/false */
#define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
#define GD32_DMA_NO_PERIPH_ADDR_INC GD32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
#define GD32_DMA_PERIPH_ADDR_INC GD32_DMA_CH_CFG_PERIPH_ADDR_INC(1)
/* memory increase defined on bit 10 as true/false */
#define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10)
#define GD32_DMA_NO_MEMORY_ADDR_INC GD32_DMA_CH_CFG_MEMORY_ADDR_INC(0)
#define GD32_DMA_MEMORY_ADDR_INC GD32_DMA_CH_CFG_MEMORY_ADDR_INC(1)
/* periph data size defined on bits 11-12 */
#define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
#define GD32_DMA_PERIPH_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
#define GD32_DMA_PERIPH_WIDTH_16BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
#define GD32_DMA_PERIPH_WIDTH_32BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
/* memory data size defined on bits 13-14 */
#define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
#define GD32_DMA_MEMORY_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
#define GD32_DMA_MEMORY_WIDTH_16BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
#define GD32_DMA_MEMORY_WIDTH_32BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
/* priority increment offset defined on bit 15 */
#define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15)
/* priority defined on bits 16-17 as 0, 1, 2, 3 */
#define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
#define GD32_DMA_PRIORITY_LOW GD32_DMA_CH_CFG_PRIORITY(0)
#define GD32_DMA_PRIORITY_MEDIUM GD32_DMA_CH_CFG_PRIORITY(1)
#define GD32_DMA_PRIORITY_HIGH GD32_DMA_CH_CFG_PRIORITY(2)
#define GD32_DMA_PRIORITY_VERY_HIGH GD32_DMA_CH_CFG_PRIORITY(3)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_ */