drivers: sensor: bmi160: Use more constants for reg access
At present register access is a mix of constants and open-coded values in the driver. Add a few more constants to clean this up. Signed-off-by: Simon Glass <sjg@chromium.org>
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@ -56,19 +56,22 @@ static int bmi160_transceive(const struct device *dev, uint8_t reg,
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int bmi160_read(const struct device *dev, uint8_t reg_addr, uint8_t *data,
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uint8_t len)
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{
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return bmi160_transceive(dev, reg_addr | BIT(7), false, data, len);
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return bmi160_transceive(dev, reg_addr | BMI160_REG_READ, false, data,
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len);
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}
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int bmi160_byte_read(const struct device *dev, uint8_t reg_addr,
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uint8_t *byte)
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{
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return bmi160_transceive(dev, reg_addr | BIT(7), false, byte, 1);
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return bmi160_transceive(dev, reg_addr | BMI160_REG_READ, false, byte,
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1);
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}
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static int bmi160_word_read(const struct device *dev, uint8_t reg_addr,
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uint16_t *word)
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{
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if (bmi160_transceive(dev, reg_addr | BIT(7), false, word, 2) != 0) {
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if (bmi160_transceive(dev, reg_addr | BMI160_REG_READ, false, word, 2)
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!= 0) {
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return -EIO;
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}
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@ -80,7 +83,8 @@ static int bmi160_word_read(const struct device *dev, uint8_t reg_addr,
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int bmi160_byte_write(const struct device *dev, uint8_t reg_addr,
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uint8_t byte)
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{
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return bmi160_transceive(dev, reg_addr & 0x7F, true, &byte, 1);
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return bmi160_transceive(dev, reg_addr & BMI160_REG_MASK, true, &byte,
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1);
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}
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int bmi160_word_write(const struct device *dev, uint8_t reg_addr,
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@ -91,7 +95,8 @@ int bmi160_word_write(const struct device *dev, uint8_t reg_addr,
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(uint8_t)(word >> 8)
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};
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return bmi160_transceive(dev, reg_addr & 0x7F, true, tx_word, 2);
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return bmi160_transceive(dev, reg_addr & BMI160_REG_MASK, true, tx_word,
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2);
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}
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int bmi160_reg_field_update(const struct device *dev, uint8_t reg_addr,
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@ -825,7 +830,7 @@ int bmi160_init(const struct device *dev)
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k_busy_wait(1000);
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/* do a dummy read from 0x7F to activate SPI */
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if (bmi160_byte_read(dev, 0x7F, &val) < 0) {
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if (bmi160_byte_read(dev, BMI160_SPI_START, &val) < 0) {
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LOG_DBG("Cannot read from 0x7F..");
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return -EIO;
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}
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@ -96,6 +96,15 @@
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#define BMI160_REG_STEP_CONF1 0x7B
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#define BMI160_REG_CMD 0x7E
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/* This is not a real register; reading it activates SPI on the BMI160 */
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#define BMI160_SPI_START 0x7F
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#define BMI160_REG_COUNT 0x80
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/* Indicates a read operation; bit 7 is clear on write s*/
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#define BMI160_REG_READ BIT(7)
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#define BMI160_REG_MASK 0x7f
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/* bitfields */
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/* BMI160_REG_ERR */
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