kw41z: add base DTS support

This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.

Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>

arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4

@@ -11,6 +11,8 @@ config SOC
 	string
 	default mkw41z4
 
+if !HAS_DTS
+
 config NUM_IRQ_PRIO_BITS
 	int
 	default 2
@@ -19,6 +21,8 @@ config NUM_IRQS
 	int
 	default 32
 
+endif # !HAS_DTS
+
 if PINMUX
 
 config PINMUX_MCUX

arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.series

@@ -10,12 +10,16 @@ if SOC_SERIES_KINETIS_KWX
 config SOC_SERIES
 	default kwx
 
+if !HAS_DTS
+
 config SRAM_BASE_ADDRESS
 	default 0x20000000
 
 config FLASH_BASE_ADDRESS
 	default 0x00000000
 
+endif # !HAS_DTS
+
 source "arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mk*"
 
 endif # SOC_SERIES_KINETIS_KWX

boards/arm/frdm_kw41z/Kconfig.defconfig

@@ -10,11 +10,14 @@ if BOARD_FRDM_KW41Z
 config BOARD
 	default frdm_kw41z
 
+if !HAS_DTS
+
 config FLASH_SIZE
 	default 512
 
 config SRAM_SIZE
 	default 128
+endif # !HAS_DTS
 
 config OSC_XTAL0_FREQ
 	default 32000000

boards/arm/frdm_kw41z/frdm_kw41z_defconfig

@@ -9,3 +9,4 @@ CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000
 CONFIG_OSC_EXTERNAL=y
+CONFIG_HAS_DTS=y

drivers/serial/Kconfig.mcux_lpuart

@@ -27,6 +27,8 @@ config UART_MCUX_LPUART_0_NAME
 	string "UART 0 driver name"
 	default "UART_0"
 
+if !HAS_DTS
+
 config UART_MCUX_LPUART_0_IRQ_PRI
 	int "UART 0 interrupt priority"
 	default 0
@@ -35,6 +37,8 @@ config UART_MCUX_LPUART_0_BAUD_RATE
 	int "UART 0 baud rate"
 	default 115200
 
+endif # !HAS_DTS
+
 endif # UART_MCUX_LPUART_0
 
 endif # UART_MCUX_LPUART

dts/arm/Makefile

@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_HAS_DTS),y)
 dtb-$(CONFIG_BOARD_FRDM_K64F)	=	frdm_k64f.dts_compiled
+dtb-$(CONFIG_BOARD_FRDM_KW41Z)		=	frdm_kw41z.dts_compiled
 dtb-$(CONFIG_BOARD_HEXIWEAR_K64)	=	hexiwear_k64.dts_compiled
 dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL)	=	cc3200_launchxl.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_L476RG)	=	nucleo_l476rg.dts_compiled

dts/arm/armv6-m.dtsi

@@ -0,0 +1,25 @@
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&nvic>;
+		ranges;
+
+		nvic: interrupt-controller@e000e100  {
+			compatible = "arm,armv6m-nvic";
+			reg = <0xe000e100 0xc00>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		systick: timer@e000e010 {
+			compatible = "arm,armv6m-systick";
+			reg = <0xe000e010 0x10>;
+			status = "disabled";
+		};
+	};
+};
+

dts/arm/frdm_kw41z.dts

@@ -0,0 +1,28 @@
+/dts-v1/;
+
+#include "nxp_kw41z.dtsi"
+
+/ {
+	model = "NXP Freedom KW41Z board";
+	compatible = "nxp,kw41z", "nxp,mkw41z4";
+
+	aliases {
+		lpuart_0 = &lpuart0;
+		pinmux_a = &pinmux_a;
+		pinmux_b = &pinmux_b;
+		pinmux_c = &pinmux_c;
+		gpio_a = &gpioa;
+		gpio_b = &gpiob;
+		gpio_c = &gpioc;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &lpuart0;
+	};
+};
+
+&lpuart0 {
+	status = "ok";
+};

dts/arm/frdm_kw41z.fixup

@@ -0,0 +1,5 @@
+#define CONFIG_NUM_IRQS				ARM_ARMV6M_NVIC_E000E100_NUM_IRQS
+#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_ARMV6M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
+
+#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE	NXP_KW41Z_LPUART_40054000_BAUD_RATE
+#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI	NXP_KW41Z_LPUART_40054000_ZEPHYR_IRQ_PRIO

dts/arm/nxp_kw41z.dtsi

@@ -0,0 +1,191 @@
+#include "armv6-m.dtsi"
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-m0+";
+		};
+	};
+
+	sram0: memory {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x20000>;
+	};
+
+	soc {
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,kw41z-mcg";
+			reg = <0x40064000 0x13>;
+			system-clock-frequency = <48000000>;
+			clock-controller;
+		};
+
+		clock-controller@40065000 {
+			compatible = "nxp,kw41z-osc";
+			reg = <0x40065000 0x4>;
+			enable-external-reference;
+		};
+
+		rtc@4003d000 {
+			compatible = "nxp,kw41z-rtc";
+			reg = <0x4003d000 0x20>;
+			clock-frequency = <32768>;
+		};
+
+		sim: sim@40047000 {
+			compatible = "nxp,kw41z-sim";
+			reg = <0x40047000 0x1060>;
+
+			clock-controller;
+			#clock-cells = <2>;
+		};
+
+		flash0: flash@0 {
+			reg = <0 0x80000>;
+		};
+
+		lpuart0: lpuart@40054000 {
+			compatible = "nxp,kw41z-lpuart";
+			reg = <0x40054000 0x18>;
+			interrupts = <12>;
+			zephyr,irq-prio = <0>;
+
+			baud-rate = <115200>;
+			pinctrl-0 = <&lpuart0_default>;
+			pinctrl-names = "default";
+
+			status = "disabled";
+		};
+
+		pinmux_a: pinmux@40049000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x40049000 0xa4>;
+			clocks = <&sim 0x1038 9>;
+
+			spi1_default: spi1_default {
+				mosi-miso-sck-pcs0 {
+					pins = <16>, <17>, <18>, <19>;
+					function = <2>;
+				};
+			};
+		};
+
+		pinmux_b: pinmux@4004a000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x4004a000 0xa4>;
+			clocks = <&sim 0x1038 10>;
+		};
+
+		pinmux_c: pinmux@4004b000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x4004b000 0xa4>;
+			clocks = <&sim 0x1038 11>;
+
+			lpuart0_default: lpuart0_default {
+				rx-tx {
+					pins = <6>, <7>;
+					function = <4>;
+				};
+			};
+
+			lpuart0_alt1: lpuart0_alt1 {
+				rx-tx {
+					pins = <17>, <18>;
+					function = <4>;
+				};
+			};
+
+			lpuart0_alt2: lpuart0_alt2 {
+				rx-tx-cts-rts {
+					pins = <2>, <3>, <0>, <1>;
+					function = <4>;
+				};
+			};
+
+			spi0_default: spi0_default {
+				mosi-miso-clk-pcs0 {
+					pins = <18>, <17>, <16>, <19>;
+					function = <2>;
+				};
+			};
+		};
+
+		gpioa: gpio@400ff000 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff000 0x40>;
+			interrupts = <30>;
+			zephyr,irq-prio = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpiob: gpio@400ff040 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff040 0x40>;
+			interrupts = <31>;
+			zephyr,irq-prio = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpioc: gpio@400ff080 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff080 0x40>;
+			interrupts = <31>;
+			zephyr,irq-prio = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		spi0: spi@4002c000 {
+			compatible = "nxp,kw41z-spi";
+			reg = <0x4002c000 0x9C>;
+			interrupts = <10>;
+			clocks = <&sim 0x103C 12>;		/* clk gate */
+
+			cs = <&gpiob 18 0>, <&gpiob 17 0>;
+			pinctrl-0 = <&spi0_default>;
+			pinctrl-names = "default";
+		};
+
+		spi1: spi@4002d000 {
+			compatible = "nxp,kw41z-spi";
+			reg = <0x4002d000 0x9C>;
+			interrupts = <29>;
+			clocks = <&sim 0x103C 13>;		/* clk gate */
+			status = "disabled";
+		};
+
+		pwm0: pwm@40038000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x40038000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+
+		pwm1: pwm@40039000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x40039000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+
+		pwm2: pwm@4003a000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x4003a000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+	};
+};
+
+&nvic {
+	num-irqs = <32>;
+	num-irq-prio-bits = <2>;
+};

dts/arm/yaml/arm,armv6m-nvic.yaml

@@ -0,0 +1,37 @@
+---
+title: ARM Cortex M0+ NVIC Interrupt Controller
+version: 0.1
+
+description: >
+    This binding describes the ARM Cortex M0+ NVIC IRQ controller
+
+properties:
+  - compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "arm,armv6m-nvic"
+
+  - reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+  - num-irq-prio-bits:
+      category: required
+      type: int
+      description: number of bits of IRQ priorities
+      generation: define
+
+  - num-irqs:
+      category: required
+      type: int
+      description: number of interrupts controlled by controller
+      generation: define
+
+cell_prefix: IRQ
+
+"#cells":
+  - irq
+...

dts/arm/yaml/nxp,kw41z-lpuart.yaml

@@ -0,0 +1,37 @@
+---
+title: KW41Z LPUART
+id: nxp,kw41z-lpuart
+version: 0.1
+
+description: >
+    This binding gives a base representation of the KW41Z LowPower-UART
+
+inherits:
+  - !include uart.yaml
+  - !include zephyr_devices.yaml
+
+properties:
+  - compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "nxp,kw41z-lpuart"
+
+  - reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+  - interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+
+  - pinctrl-*:
+      type: array
+      category: optional
+      description: pinmux information for RX, TX, CTS, RTS
+      generation: structures
+...

dts/arm/yaml/nxp,kw41z-pinmux.yaml

@@ -0,0 +1,32 @@
+---
+title: KW41Z Pinmux
+version: 0.1
+
+description: >
+    This is a representation of the KW41Z Pinmux node
+
+properties:
+  - compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "nxp,kw41z-pinmux"
+
+  - reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+  - clocks:
+      type: array
+      description: clock gate information
+      generation: define
+      category: required
+
+cell_string: PINMUX
+
+"#cells":
+  - pin
+  - function
+...

dts/arm/yaml/nxp,kw41z-sim.yaml

@@ -0,0 +1,26 @@
+---
+title: KW41Z System Integration Module (SIM)
+version: 0.1
+
+description: >
+    This is a representation of the KW41Z SIM IP node
+
+properties:
+  - compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "nxp,kw41z-sim"
+
+  - reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+cell_string: SIM_CLK
+
+"#cells":
+  - offset
+  - bits
+...