From 5b2d80ca18b43b720f60a5744628921f14289ee3 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Mon, 12 Dec 2022 12:01:09 +0100 Subject: [PATCH] tests: drivers: stm32g0 clock control with APB1_2 RCC register Change the name of the STM32_CLOCK_BUS_APB2 RCC resgister of the stm32g0 to STM32_CLOCK_BUS_APB1_2 in the testcase for the stm32g0 device. Signed-off-by: Francois Ramu --- .../boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay index 0737e15487..ee2d70a1e0 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay @@ -77,7 +77,7 @@ }; &adc1 { - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>, + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>, <&rcc STM32_SRC_PLL_P ADC_SEL(1)>; status = "okay"; };