xtensa: fix inline assembly of rsil in exception code for XCC

Commit 408472673e added inline
assembly to lock interrupt. However, XCC doesn't like the syntax
using STRINGIFY, and also an empty clobber section. So parameterize
the second argument to rsil, and remove the last colon.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

arch/xtensa/core/xtensa-asm2.c

@@ -330,8 +330,8 @@ void *xtensa_excint1_c(int *interrupted_stack)
 		 *    resulting it being zero before switching to another
 		 *    thread.
 		 */
-		__asm__ volatile("rsil %0, " STRINGIFY(XCHAL_NMILEVEL)
-				: "=r" (ignore) : : );
+		__asm__ volatile("rsil %0, %1"
+				: "=r" (ignore) : "i"(XCHAL_NMILEVEL));
 
 		_current_cpu->nested = 1;
 	}