tests: drivers: adc: adc_api: add dma test

Move ADC DMA tests directly into adc_api test for Kinetis and STM32 boards.
Needs to disable CONFIG_TEST_USERSPACE for this subtest because of caching
issue for STM32H7 (as it was done dor adc_dma test).

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2024-02-23 14:22:58 +01:00 committed by Alberto Escolar
parent b8e5ac18f1
commit 5eb045dc83
12 changed files with 168 additions and 3 deletions

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@ -0,0 +1,12 @@
# ADC API test configuration options
# Copyright (c) 2024 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
mainmenu "ADC API Test"
source "Kconfig.zephyr"
config ADC_API_SAMPLE_INTERVAL_US
int "Interval between repeatead samples in us"
default 0

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@ -13,6 +13,11 @@
&adc0 { &adc0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clk-source = <0>;
hw-trigger-src = <4>;
continuous-convert;
high-speed;
periodic-trigger;
status = "okay"; status = "okay";
channel@e { channel@e {
@ -23,3 +28,11 @@
zephyr,resolution = <12>; zephyr,resolution = <12>;
}; };
}; };
test_counter: &pit0_channel0 {
status = "okay";
};
&edma0 {
dma-buf-addr-alignment = <4>;
};

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@ -13,6 +13,11 @@
&adc0 { &adc0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clk-source = <0>;
hw-trigger-src = <4>;
continuous-convert;
high-speed;
periodic-trigger;
status = "okay"; status = "okay";
channel@f { channel@f {
@ -23,3 +28,11 @@
zephyr,resolution = <12>; zephyr,resolution = <12>;
}; };
}; };
test_counter: &pit0_channel0 {
status = "okay";
};
&edma0 {
dma-buf-addr-alignment = <4>;
};

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@ -12,6 +12,10 @@
}; };
&adc1 { &adc1 {
dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>;
dma-names = "dma";
pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -32,3 +36,7 @@
zephyr,resolution = <12>; zephyr,resolution = <12>;
}; };
}; };
&dma2 {
status = "okay";
};

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@ -0,0 +1 @@
CONFIG_NOCACHE_MEMORY=y

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@ -4,6 +4,8 @@
* Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com> * Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
*/ */
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
/ { / {
zephyr,user { zephyr,user {
/* adjust channel number according to pinmux in board.dts */ /* adjust channel number according to pinmux in board.dts */
@ -11,7 +13,15 @@
}; };
}; };
&sram2 {
zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
};
&adc1 { &adc1 {
dmas = <&dmamux1 0 9 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
STM32_DMA_PERIPH_16BITS)>;
dma-names = "dmamux";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -31,3 +41,15 @@
zephyr,resolution = <16>; zephyr,resolution = <16>;
}; };
}; };
&dma1 {
status = "okay";
};
&dma2 {
status = "okay";
};
&dmamux1 {
status = "okay";
};

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@ -12,6 +12,9 @@
}; };
&adc1 { &adc1 {
dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
dma-names = "dma";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -23,3 +26,7 @@
zephyr,resolution = <10>; zephyr,resolution = <10>;
}; };
}; };
&dma1 {
status = "okay";
};

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@ -12,6 +12,9 @@
}; };
&adc1 { &adc1 {
dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
dma-names = "gpdma";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -23,3 +26,7 @@
zephyr,resolution = <12>; zephyr,resolution = <12>;
}; };
}; };
&gpdma1 {
status = "okay";
};

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@ -0,0 +1,13 @@
#
# Copyright (c) 2020, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_TEST_USERSPACE=n
CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA=y
CONFIG_ADC_MCUX_ADC16_HW_TRIGGER=y
CONFIG_COUNTER=y
CONFIG_ADC_ASYNC=y
CONFIG_DMA=y
CONFIG_ADC_API_SAMPLE_INTERVAL_US=30000

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@ -0,0 +1,8 @@
#
# Copyright (c) 2024 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_TEST_USERSPACE=n
CONFIG_ADC_STM32_DMA=y

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@ -7,6 +7,8 @@
#include <zephyr/drivers/adc.h> #include <zephyr/drivers/adc.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/counter.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/ztest.h> #include <zephyr/ztest.h>
@ -18,8 +20,18 @@
#define INVALID_ADC_VALUE SHRT_MIN #define INVALID_ADC_VALUE SHRT_MIN
#endif #endif
#if CONFIG_NOCACHE_MEMORY
#define __NOCACHE __attribute__((__section__(".nocache")))
#else /* CONFIG_NOCACHE_MEMORY */
#define __NOCACHE
#endif /* CONFIG_NOCACHE_MEMORY */
#define BUFFER_SIZE 6 #define BUFFER_SIZE 6
#ifdef CONFIG_TEST_USERSPACE
static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE]; static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE];
#else
static __aligned(32) int16_t m_sample_buffer[BUFFER_SIZE] __NOCACHE;
#endif
#define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx), #define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx),
@ -43,6 +55,26 @@ const struct device *get_adc_device(void)
return adc_channels[0].dev; return adc_channels[0].dev;
} }
#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \
defined(CONFIG_COUNTER)
static void init_counter(void)
{
int err;
const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(test_counter));
struct counter_top_cfg top_cfg = { .callback = NULL,
.user_data = NULL,
.flags = 0 };
zassert_true(device_is_ready(dev), "Counter device is not ready");
counter_start(dev);
top_cfg.ticks = counter_us_to_ticks(dev, CONFIG_ADC_API_SAMPLE_INTERVAL_US);
err = counter_set_top_value(dev, &top_cfg);
zassert_equal(0, err, "%s: Counter failed to set top value (err: %d)",
dev->name, err);
}
#endif
static void init_adc(void) static void init_adc(void)
{ {
int i, ret; int i, ret;
@ -57,6 +89,11 @@ static void init_adc(void)
for (i = 0; i < BUFFER_SIZE; ++i) { for (i = 0; i < BUFFER_SIZE; ++i) {
m_sample_buffer[i] = INVALID_ADC_VALUE; m_sample_buffer[i] = INVALID_ADC_VALUE;
} }
#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \
defined(CONFIG_COUNTER)
init_counter();
#endif
} }
static void check_samples(int expected_count) static void check_samples(int expected_count)
@ -156,7 +193,7 @@ static int test_task_asynchronous_call(void)
const struct adc_sequence_options options = { const struct adc_sequence_options options = {
.extra_samplings = 4, .extra_samplings = 4,
/* Start consecutive samplings as fast as possible. */ /* Start consecutive samplings as fast as possible. */
.interval_us = 0, .interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US,
}; };
struct adc_sequence sequence = { struct adc_sequence sequence = {
.options = &options, .options = &options,
@ -295,7 +332,7 @@ static int test_task_repeated_samplings(void)
*/ */
.extra_samplings = 2, .extra_samplings = 2,
/* Start consecutive samplings as fast as possible. */ /* Start consecutive samplings as fast as possible. */
.interval_us = 0, .interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US,
}; };
struct adc_sequence sequence = { struct adc_sequence sequence = {
.options = &options, .options = &options,

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@ -9,6 +9,30 @@ tests:
min_flash: 40 min_flash: 40
drivers.adc.b_u585i_iot02a_adc4: drivers.adc.b_u585i_iot02a_adc4:
extra_args: extra_args:
DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay" - DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay"
platform_allow: platform_allow:
- b_u585i_iot02a - b_u585i_iot02a
drivers.adc.dma_st_stm32:
extra_args:
- OVERLAY_CONFIG="overlay-dma-stm32.conf"
depends_on:
- adc
- dma
min_flash: 40
platform_allow:
- nucleo_f401re
- nucleo_h743zi
- nucleo_l476rg
- nucleo_u575zi_q
drivers.adc.dma_nxp_kinetis:
extra_args:
- OVERLAY_CONFIG="overlay-dma-kinetis.conf"
depends_on:
- adc
- dma
min_flash: 40
platform_allow:
- frdm_k64f
- frdm_k82f
integration_platforms:
- frdm_k82f