tests: drivers: adc: adc_api: add dma test
Move ADC DMA tests directly into adc_api test for Kinetis and STM32 boards. Needs to disable CONFIG_TEST_USERSPACE for this subtest because of caching issue for STM32H7 (as it was done dor adc_dma test). Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
parent
b8e5ac18f1
commit
5eb045dc83
12
tests/drivers/adc/adc_api/Kconfig
Normal file
12
tests/drivers/adc/adc_api/Kconfig
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@ -0,0 +1,12 @@
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# ADC API test configuration options
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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mainmenu "ADC API Test"
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source "Kconfig.zephyr"
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config ADC_API_SAMPLE_INTERVAL_US
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int "Interval between repeatead samples in us"
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default 0
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@ -13,6 +13,11 @@
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&adc0 {
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&adc0 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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clk-source = <0>;
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hw-trigger-src = <4>;
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continuous-convert;
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high-speed;
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periodic-trigger;
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status = "okay";
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status = "okay";
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channel@e {
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channel@e {
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@ -23,3 +28,11 @@
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zephyr,resolution = <12>;
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zephyr,resolution = <12>;
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};
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};
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};
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};
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test_counter: &pit0_channel0 {
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status = "okay";
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};
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&edma0 {
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dma-buf-addr-alignment = <4>;
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};
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@ -13,6 +13,11 @@
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&adc0 {
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&adc0 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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clk-source = <0>;
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hw-trigger-src = <4>;
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continuous-convert;
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high-speed;
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periodic-trigger;
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status = "okay";
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status = "okay";
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channel@f {
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channel@f {
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@ -23,3 +28,11 @@
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zephyr,resolution = <12>;
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zephyr,resolution = <12>;
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};
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};
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};
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};
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test_counter: &pit0_channel0 {
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status = "okay";
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};
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&edma0 {
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dma-buf-addr-alignment = <4>;
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};
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@ -12,6 +12,10 @@
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};
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};
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&adc1 {
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&adc1 {
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dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
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STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>;
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dma-names = "dma";
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pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>;
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pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>;
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -32,3 +36,7 @@
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zephyr,resolution = <12>;
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zephyr,resolution = <12>;
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};
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};
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};
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};
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&dma2 {
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status = "okay";
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};
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1
tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf
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1
tests/drivers/adc/adc_api/boards/nucleo_h743zi.conf
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@ -0,0 +1 @@
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CONFIG_NOCACHE_MEMORY=y
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@ -4,6 +4,8 @@
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* Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
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* Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
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*/
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*/
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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/ {
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zephyr,user {
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zephyr,user {
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/* adjust channel number according to pinmux in board.dts */
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/* adjust channel number according to pinmux in board.dts */
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@ -11,7 +13,15 @@
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};
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};
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};
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};
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&sram2 {
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zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
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};
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&adc1 {
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&adc1 {
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dmas = <&dmamux1 0 9 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
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STM32_DMA_PERIPH_16BITS)>;
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dma-names = "dmamux";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -31,3 +41,15 @@
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zephyr,resolution = <16>;
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zephyr,resolution = <16>;
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};
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};
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};
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};
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&dma1 {
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status = "okay";
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};
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&dma2 {
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status = "okay";
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};
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&dmamux1 {
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status = "okay";
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};
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@ -12,6 +12,9 @@
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};
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};
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&adc1 {
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&adc1 {
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dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
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dma-names = "dma";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -23,3 +26,7 @@
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zephyr,resolution = <10>;
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zephyr,resolution = <10>;
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};
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};
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};
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};
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&dma1 {
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status = "okay";
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};
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@ -12,6 +12,9 @@
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};
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};
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&adc1 {
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&adc1 {
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dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
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dma-names = "gpdma";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -23,3 +26,7 @@
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zephyr,resolution = <12>;
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zephyr,resolution = <12>;
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};
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};
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};
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};
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&gpdma1 {
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status = "okay";
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};
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13
tests/drivers/adc/adc_api/overlay-dma-kinetis.conf
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13
tests/drivers/adc/adc_api/overlay-dma-kinetis.conf
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@ -0,0 +1,13 @@
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#
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# Copyright (c) 2020, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_TEST_USERSPACE=n
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CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA=y
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CONFIG_ADC_MCUX_ADC16_HW_TRIGGER=y
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CONFIG_COUNTER=y
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CONFIG_ADC_ASYNC=y
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CONFIG_DMA=y
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CONFIG_ADC_API_SAMPLE_INTERVAL_US=30000
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8
tests/drivers/adc/adc_api/overlay-dma-stm32.conf
Normal file
8
tests/drivers/adc/adc_api/overlay-dma-stm32.conf
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@ -0,0 +1,8 @@
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#
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# Copyright (c) 2024 STMicroelectronics
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_TEST_USERSPACE=n
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CONFIG_ADC_STM32_DMA=y
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@ -7,6 +7,8 @@
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/kernel.h>
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#include <zephyr/kernel.h>
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#include <zephyr/ztest.h>
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#include <zephyr/ztest.h>
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#define INVALID_ADC_VALUE SHRT_MIN
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#define INVALID_ADC_VALUE SHRT_MIN
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#endif
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#endif
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#if CONFIG_NOCACHE_MEMORY
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#define __NOCACHE __attribute__((__section__(".nocache")))
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#else /* CONFIG_NOCACHE_MEMORY */
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#define __NOCACHE
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#endif /* CONFIG_NOCACHE_MEMORY */
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#define BUFFER_SIZE 6
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#define BUFFER_SIZE 6
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#ifdef CONFIG_TEST_USERSPACE
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static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE];
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static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE];
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#else
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static __aligned(32) int16_t m_sample_buffer[BUFFER_SIZE] __NOCACHE;
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#endif
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#define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx),
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#define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx),
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@ -43,6 +55,26 @@ const struct device *get_adc_device(void)
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return adc_channels[0].dev;
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return adc_channels[0].dev;
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}
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}
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \
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defined(CONFIG_COUNTER)
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static void init_counter(void)
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{
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int err;
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(test_counter));
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struct counter_top_cfg top_cfg = { .callback = NULL,
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.user_data = NULL,
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.flags = 0 };
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zassert_true(device_is_ready(dev), "Counter device is not ready");
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counter_start(dev);
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top_cfg.ticks = counter_us_to_ticks(dev, CONFIG_ADC_API_SAMPLE_INTERVAL_US);
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err = counter_set_top_value(dev, &top_cfg);
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zassert_equal(0, err, "%s: Counter failed to set top value (err: %d)",
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dev->name, err);
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}
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#endif
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static void init_adc(void)
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static void init_adc(void)
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{
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{
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int i, ret;
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int i, ret;
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@ -57,6 +89,11 @@ static void init_adc(void)
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for (i = 0; i < BUFFER_SIZE; ++i) {
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for (i = 0; i < BUFFER_SIZE; ++i) {
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m_sample_buffer[i] = INVALID_ADC_VALUE;
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m_sample_buffer[i] = INVALID_ADC_VALUE;
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}
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}
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(test_counter), okay) && \
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defined(CONFIG_COUNTER)
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init_counter();
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#endif
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}
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}
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static void check_samples(int expected_count)
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static void check_samples(int expected_count)
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@ -156,7 +193,7 @@ static int test_task_asynchronous_call(void)
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const struct adc_sequence_options options = {
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const struct adc_sequence_options options = {
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.extra_samplings = 4,
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.extra_samplings = 4,
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/* Start consecutive samplings as fast as possible. */
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/* Start consecutive samplings as fast as possible. */
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.interval_us = 0,
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.interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US,
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};
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};
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struct adc_sequence sequence = {
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struct adc_sequence sequence = {
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.options = &options,
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.options = &options,
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@ -295,7 +332,7 @@ static int test_task_repeated_samplings(void)
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*/
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*/
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.extra_samplings = 2,
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.extra_samplings = 2,
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/* Start consecutive samplings as fast as possible. */
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/* Start consecutive samplings as fast as possible. */
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.interval_us = 0,
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.interval_us = CONFIG_ADC_API_SAMPLE_INTERVAL_US,
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};
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};
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struct adc_sequence sequence = {
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struct adc_sequence sequence = {
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.options = &options,
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.options = &options,
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@ -9,6 +9,30 @@ tests:
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min_flash: 40
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min_flash: 40
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drivers.adc.b_u585i_iot02a_adc4:
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drivers.adc.b_u585i_iot02a_adc4:
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extra_args:
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extra_args:
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DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay"
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- DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay"
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platform_allow:
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platform_allow:
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- b_u585i_iot02a
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- b_u585i_iot02a
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drivers.adc.dma_st_stm32:
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extra_args:
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- OVERLAY_CONFIG="overlay-dma-stm32.conf"
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depends_on:
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- adc
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- dma
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min_flash: 40
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platform_allow:
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- nucleo_f401re
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- nucleo_h743zi
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- nucleo_l476rg
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- nucleo_u575zi_q
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drivers.adc.dma_nxp_kinetis:
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extra_args:
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- OVERLAY_CONFIG="overlay-dma-kinetis.conf"
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depends_on:
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- adc
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- dma
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min_flash: 40
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platform_allow:
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- frdm_k64f
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- frdm_k82f
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integration_platforms:
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- frdm_k82f
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