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soc: lpc54xxx: align to lpc55xxx multicore defs

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Aligns lpc54xxx Kconfigs and other definitions to lpc55xxx.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit is contained in:
Andrei Gansari 2020-12-16 18:54:03 +02:00 committed by Anas Nashif
parent e8a35231a2
commit 5ed37c61a9
3 changed files with 20 additions and 20 deletions
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8
soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt
View file

@ -12,14 +12,14 @@ zephyr_library_include_directories(
${ZEPHYR_BASE}/arch/${ARCH}/include
)
if (CONFIG_SLAVE_CORE_MCUX)
if (CONFIG_SECOND_CORE_MCUX)
set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)
string(CONFIGURE ${CONFIG_SLAVE_IMAGE_MCUX} core_m0_image)
string(CONFIGURE ${CONFIG_SECOND_IMAGE_MCUX} core_m0_image)
add_custom_target(core_m0_inc_target DEPENDS ${gen_dir}/core-m0.inc)
add_custom_target(second_core_inc_target DEPENDS ${gen_dir}/core-m0.inc)
generate_inc_file_for_gen_target(${ZEPHYR_CURRENT_LIBRARY}
${core_m0_image}
${gen_dir}/core-m0.inc
core_m0_inc_target)
second_core_inc_target)
endif()

26
soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc
View file

@ -37,26 +37,26 @@ config SOC_PART_NUMBER_LPC54XXX
option that you should not set directly. The part number selection
choice defines the default value for this string.
config SLAVE_CORE_MCUX
bool "Enable LPC54114 Cortex-M0 slave core"
config SECOND_CORE_MCUX
bool "Enable LPC54114 Cortex-M0 second core"
depends on HAS_MCUX
help
Driver for slave core startup
Driver for second core startup
config SLAVE_IMAGE_MCUX
depends on SLAVE_CORE_MCUX
string "Binary image of slave core's code"
config SECOND_IMAGE_MCUX
depends on SECOND_CORE_MCUX
string "Binary image of second core's code"
help
This points to the image file for the the binary code that will be
used by the slave core.
used by the second core.
config SLAVE_BOOT_ADDRESS_MCUX
depends on SLAVE_CORE_MCUX
hex "Address the slave core will boot at"
config SECOND_CORE_BOOT_ADDRESS_MCUX
depends on SECOND_CORE_MCUX
hex "Address the second core will boot at"
default 0x20010000
help
This is the address the slave core will boot from. Additionally this
address is where we will copy the SLAVE_IMAGE to. We default this to
the base of SRAM1
This is the address the second core will boot from. Additionally this
address is where we will copy the SECOND_IMAGE to. We default this to
the base of SRAM1.
endif # SOC_SERIES_LPC54XXX

6
soc/arm/nxp_lpc/lpc54xxx/soc.c
View file

@ -129,9 +129,9 @@ static int nxp_lpc54114_init(const struct device *arg)
SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
#ifdef CONFIG_SLAVE_CORE_MCUX
#ifdef CONFIG_SECOND_CORE_MCUX
#define CORE_M0_BOOT_ADDRESS (void *)CONFIG_SLAVE_BOOT_ADDRESS_MCUX
#define CORE_M0_BOOT_ADDRESS ((void *)CONFIG_SECOND_CORE_BOOT_ADDRESS_MCUX)
static const char core_m0[] = {
#include "core-m0.inc"
@ -184,4 +184,4 @@ int _slave_init(const struct device *arg)
SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /*CONFIG_SLAVE_CORE_MCUX*/
#endif /*CONFIG_SECOND_CORE_MCUX*/