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soc: arc: synopsys: move secure timer0 definition to DT

Browse source 
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.

DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:

- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-06-15 13:24:21 +02:00 committed by Anas Nashif
parent 44250fe3d3
commit 5f40a9f40f
11 changed files with 47 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
boards/arc/em_starterkit/em_starterkit_em7d.dts
View file

@ -7,7 +7,7 @@
/dts-v1/;
#include <mem.h>
#include <synopsys/emsk.dtsi>
#include <synopsys/emsk-sec.dtsi>
#include "em_starterkit_r23.dtsi"
#include "board.dtsi"

2
boards/arc/emsdp/emsdp_em7d_esp.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <synopsys/emsdp.dtsi>
#include <synopsys/emsdp-sec.dtsi>
#include "board.dtsi"
/ {

14
boards/arc/nsim/nsim_em-sec.dtsi Normal file
View file

@ -0,0 +1,14 @@
/*
* Copyright (c) 2022 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include "nsim_em.dtsi"
/ {
sectimer0: sectimer0 {
compatible = "snps,arc-timer";
interrupts = <20 1>;
interrupt-parent = <&intc>;
};
};

2
boards/arc/nsim/nsim_sem.dts
View file

@ -7,7 +7,7 @@
/dts-v1/;
#include "nsim_em.dtsi"
#include "nsim_em-sec.dtsi"
/ {

2
boards/arc/nsim/nsim_sem_mpu_stack_guard.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "nsim_em.dtsi"
#include "nsim_em-sec.dtsi"
/ {
model = "snps,nsim_sem_mpu_stack_guard";

2
drivers/timer/arcv2_timer0.c
View file

@ -27,7 +27,7 @@
#define _ARC_V2_TMR0_COUNT _ARC_V2_S_TMR0_COUNT
#define _ARC_V2_TMR0_CONTROL _ARC_V2_S_TMR0_CONTROL
#define _ARC_V2_TMR0_LIMIT _ARC_V2_S_TMR0_LIMIT
#define IRQ_TIMER0 IRQ_SEC_TIMER0
#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(sectimer0))
#else
#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(timer0))

14
dts/arc/synopsys/emsdp-sec.dtsi Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2022 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include "emsdp.dtsi"
/ {
sectimer0: sectimer0 {
compatible = "snps,arc-timer";
interrupts = <20 1>;
interrupt-parent = <&intc>;
};
};

14
dts/arc/synopsys/emsk-sec.dtsi Normal file
View file

@ -0,0 +1,14 @@
/*
* Copyright (c) 2022 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include "emsk.dtsi"
/ {
sectimer0: sectimer0 {
compatible = "snps,arc-timer";
interrupts = <20 1>;
interrupt-parent = <&intc>;
};
};

3
soc/arc/snps_emsdp/soc.h
View file

@ -19,9 +19,6 @@
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(100)
/* ARC EM Core IRQs */
#define IRQ_SEC_TIMER0 20
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>

5
soc/arc/snps_emsk/soc.h
View file

@ -20,11 +20,6 @@
/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
/* ARC EM Core IRQs */
#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D)
#define IRQ_SEC_TIMER0 20
#endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D */
#if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D)
#define IRQ_CORE_DMA_COMPLETE 22
#define IRQ_CORE_DMA_ERROR 23

3
soc/arc/snps_nsim/soc.h
View file

@ -16,9 +16,6 @@
#include <zephyr/sys/util.h>
/* ARC EM Core IRQs */
#define IRQ_SEC_TIMER0 20
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>