drivers/disk: sdmmc: Add DMA support.
This fixes underrun issues when hardware flow control can't be used. Only tested on STM32F4. Signed-off-by: John Kjellberg <kjellberg.john@gmail.com> ...
This commit is contained in:
John Kjellberg
Carles Cufí
parent
6825d84123
commit
6076991fdb
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@ -4,6 +4,7 @@
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DT_COMPAT_ST_STM32_SDMMC := st,stm32-sdmmc
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DT_COMPAT_ZEPHYR_MMC := zephyr,sdmmc-disk
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DT_STM32_SDMMC_HAS_DMA := $(dt_nodelabel_has_prop,sdmmc,dmas)
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config DISK_DRIVER_SDMMC
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bool "SDMMC card driver"
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@ -40,6 +41,7 @@ config SDMMC_STM32
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select USE_STM32_HAL_SD_EX if SOC_SERIES_STM32L4X
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select USE_STM32_LL_SDMMC
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select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X)
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select DMA if ($(DT_STM32_SDMMC_HAS_DMA) && SOC_SERIES_STM32F4X)
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default $(dt_compat_enabled,$(DT_COMPAT_ST_STM32_SDMMC))
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help
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File system on sdmmc accessed through stm32 sdmmc.
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@ -18,6 +18,14 @@
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LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL);
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#define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas)
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#if STM32_SDMMC_USE_DMA
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_stm32.h>
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#include <stm32_ll_dma.h>
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#endif
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#ifndef MMC_TypeDef
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#define MMC_TypeDef SDMMC_TypeDef
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#endif
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@ -36,6 +44,24 @@ LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL);
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typedef void (*irq_config_func_t)(const struct device *dev);
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#if STM32_SDMMC_USE_DMA
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uint32_t table_priority[] = {
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DMA_PRIORITY_LOW,
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DMA_PRIORITY_MEDIUM,
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DMA_PRIORITY_HIGH,
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DMA_PRIORITY_VERY_HIGH
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};
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struct sdmmc_dma_stream {
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const struct device *dev;
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uint32_t channel;
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uint32_t channel_nb;
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DMA_TypeDef *reg;
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struct dma_config cfg;
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};
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#endif
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struct stm32_sdmmc_priv {
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irq_config_func_t irq_config;
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struct k_sem thread_lock;
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@ -48,6 +74,11 @@ struct stm32_sdmmc_priv {
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struct gpio_dt_spec pe;
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struct stm32_pclken pclken;
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const struct pinctrl_dev_config *pcfg;
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#if STM32_SDMMC_USE_DMA
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struct sdmmc_dma_stream dma_rx;
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struct sdmmc_dma_stream dma_tx;
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#endif
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};
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#ifdef CONFIG_SDMMC_STM32_HWFC
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@ -136,6 +167,85 @@ static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
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(clock_control_subsys_t *)&priv->pclken);
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}
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#if STM32_SDMMC_USE_DMA
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static void stm32_sdmmc_dma_cb(const struct device *dev, void *arg,
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uint32_t channel, int status)
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{
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DMA_HandleTypeDef *hdma = arg;
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if (status != 0) {
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LOG_ERR("DMA callback error with channel %d.", channel);
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}
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HAL_DMA_IRQHandler(hdma);
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}
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static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma_stream *dma)
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{
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int ret;
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if (!device_is_ready(dma->dev)) {
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LOG_ERR("Failed to get dma dev");
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return -ENODEV;
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}
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dma->cfg.user_data = handle;
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ret = dma_config(dma->dev, dma->channel, &dma->cfg);
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if (ret != 0) {
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LOG_ERR("Failed to conig");
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return ret;
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}
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handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb);
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handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1;
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handle->Init.PeriphInc = DMA_PINC_DISABLE;
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handle->Init.MemInc = DMA_MINC_ENABLE;
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handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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handle->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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handle->Init.Mode = DMA_PFCTRL;
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handle->Init.Priority = table_priority[dma->cfg.channel_priority],
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handle->Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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handle->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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handle->Init.MemBurst = DMA_MBURST_INC4;
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handle->Init.PeriphBurst = DMA_PBURST_INC4;
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return ret;
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}
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static int stm32_sdmmc_dma_init(struct stm32_sdmmc_priv *priv)
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{
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static DMA_HandleTypeDef dma_tx_handle;
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static DMA_HandleTypeDef dma_rx_handle;
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int err;
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LOG_DBG("using dma");
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err = stm32_sdmmc_configure_dma(&dma_tx_handle, &priv->dma_tx);
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if (err) {
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LOG_ERR("failed to init tx dma");
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return err;
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}
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__HAL_LINKDMA(&priv->hsd, hdmatx, dma_tx_handle);
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HAL_DMA_DeInit(&dma_tx_handle);
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HAL_DMA_Init(&dma_tx_handle);
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stm32_sdmmc_configure_dma(&dma_rx_handle, &priv->dma_rx);
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if (err) {
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LOG_ERR("failed to init rx dma");
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return err;
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}
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__HAL_LINKDMA(&priv->hsd, hdmarx, dma_rx_handle);
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HAL_DMA_DeInit(&dma_rx_handle);
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HAL_DMA_Init(&dma_rx_handle);
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return err;
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}
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#endif
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static int stm32_sdmmc_access_init(struct disk_info *disk)
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{
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const struct device *dev = disk->dev;
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@ -150,6 +260,10 @@ static int stm32_sdmmc_access_init(struct disk_info *disk)
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return -ENODEV;
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}
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#if STM32_SDMMC_USE_DMA
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stm32_sdmmc_dma_init(priv);
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#endif
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err = stm32_sdmmc_clock_enable(priv);
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if (err) {
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LOG_ERR("failed to init clocks");
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@ -193,8 +307,13 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
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k_sem_take(&priv->thread_lock, K_FOREVER);
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#if STM32_SDMMC_USE_DMA
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err = HAL_SD_ReadBlocks_DMA(&priv->hsd, data_buf, start_sector,
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num_sector);
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#else
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err = HAL_SD_ReadBlocks_IT(&priv->hsd, data_buf, start_sector,
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num_sector);
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#endif
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if (err != HAL_OK) {
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LOG_ERR("sd read block failed %d", err);
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err = -EIO;
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@ -227,8 +346,13 @@ static int stm32_sdmmc_access_write(struct disk_info *disk,
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k_sem_take(&priv->thread_lock, K_FOREVER);
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#if STM32_SDMMC_USE_DMA
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err = HAL_SD_WriteBlocks_DMA(&priv->hsd, (uint8_t *)data_buf, start_sector,
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num_sector);
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#else
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err = HAL_SD_WriteBlocks_IT(&priv->hsd, (uint8_t *)data_buf, start_sector,
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num_sector);
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#endif
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if (err != HAL_OK) {
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LOG_ERR("sd write block failed %d", err);
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err = -EIO;
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@ -486,6 +610,35 @@ err_card_detect:
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
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#if STM32_SDMMC_USE_DMA
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#define SDMMC_DMA_CHANNEL_INIT(dir, dir_cap) \
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.dev = DEVICE_DT_GET(STM32_DMA_CTLR(0, dir)), \
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.channel = DT_INST_DMAS_CELL_BY_NAME(0, dir, channel), \
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.channel_nb = DT_DMAS_CELL_BY_NAME( \
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DT_DRV_INST(0), dir, channel), \
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.reg = (DMA_TypeDef *)DT_REG_ADDR( \
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DT_PHANDLE_BY_NAME(DT_DRV_INST(0), dmas, dir)), \
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.cfg = { \
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.dma_slot = STM32_DMA_SLOT(0, dir, slot), \
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.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
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STM32_DMA_CHANNEL_CONFIG(0, dir)), \
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.dma_callback = stm32_sdmmc_dma_cb, \
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.linked_channel = STM32_DMA_HAL_OVERRIDE, \
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}, \
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#define SDMMC_DMA_CHANNEL(dir, DIR) \
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.dma_##dir = { \
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COND_CODE_1(DT_INST_DMAS_HAS_NAME(0, dir), \
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(SDMMC_DMA_CHANNEL_INIT(dir, DIR)), \
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(NULL)) \
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},
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#else
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#define SDMMC_DMA_CHANNEL(dir, DIR)
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#endif
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PINCTRL_DT_INST_DEFINE(0);
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static void stm32_sdmmc_irq_config_func(const struct device *dev)
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@ -522,6 +675,8 @@ static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = {
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.enr = DT_INST_CLOCKS_CELL(0, bits),
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},
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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SDMMC_DMA_CHANNEL(rx, RX)
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SDMMC_DMA_CHANNEL(tx, TX)
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};
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DEVICE_DT_INST_DEFINE(0, disk_stm32_sdmmc_init, NULL,
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@ -38,3 +38,22 @@ properties:
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- 1
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- 4
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- 8
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dmas:
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description: |
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Optional DMA channel specifier. If DMA should be used, specifier should
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hold a phandle reference to the dma controller, the channel number,
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the slot number, channel configuration and finally features.
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Only priority bits are used in the configuration. There are no feature
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flags.
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For example dmas for TX/RX on SDMMC
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dmas = <&dma2 4 6 0x30000 0x00>, <&dma2 4 3 0x30000 0x00>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx", "rx".
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For example
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dma-names = "tx", "rx";
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