diff --git a/arch/arc/soc/em11d/Kconfig.defconfig b/arch/arc/soc/em11d/Kconfig.defconfig index 58d26f5052..85c4345021 100644 --- a/arch/arc/soc/em11d/Kconfig.defconfig +++ b/arch/arc/soc/em11d/Kconfig.defconfig @@ -29,31 +29,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config HARVARD def_bool n -config FLASH_BASE_ADDRESS - default 0x00000000 - -config FLASH_SIZE - default 0 - # em11d has no FLASH so size is 0. - -config SRAM_BASE_ADDRESS - default 0x10000000 - -config SRAM_SIZE - default 131072 - -config ICCM_BASE_ADDRESS - default 0x00000000 - -config ICCM_SIZE - default 64 - -config DCCM_BASE_ADDRESS - default 0x80000000 - -config DCCM_SIZE - default 64 - config CACHE_FLUSHING def_bool y diff --git a/arch/arc/soc/em11d/dts.fixup b/arch/arc/soc/em11d/dts.fixup new file mode 100644 index 0000000000..e61cb01e5e --- /dev/null +++ b/arch/arc/soc/em11d/dts.fixup @@ -0,0 +1,9 @@ +/* SoC level DTS fixup file */ + +#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS +#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10) + +#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS +#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) + +/* End of SoC Level DTS fixup file */ diff --git a/arch/arc/soc/em11d/linker.ld b/arch/arc/soc/em11d/linker.ld index 805a38744e..ff0fea7aea 100644 --- a/arch/arc/soc/em11d/linker.ld +++ b/arch/arc/soc/em11d/linker.ld @@ -29,4 +29,5 @@ #define DCCM_START CONFIG_DCCM_BASE_ADDRESS #define DCCM_SIZE CONFIG_DCCM_SIZE +#include #include diff --git a/arch/arc/soc/em7d/Kconfig.defconfig b/arch/arc/soc/em7d/Kconfig.defconfig index 9d9020aab8..7f5bec92e7 100644 --- a/arch/arc/soc/em7d/Kconfig.defconfig +++ b/arch/arc/soc/em7d/Kconfig.defconfig @@ -38,31 +38,6 @@ config ARC_FIRQ def_bool n if BOARD_EM_STARTERKIT_R23 def_bool y if BOARD_EM_STARTERKIT_R22 -config FLASH_BASE_ADDRESS - default 0x00000000 - -config FLASH_SIZE - default 0 - # em7d has no FLASH so size is 0. - -config SRAM_BASE_ADDRESS - default 0x10000000 - -config SRAM_SIZE - default 131072 - -config ICCM_BASE_ADDRESS - default 0x00000000 - -config ICCM_SIZE - default 256 - -config DCCM_BASE_ADDRESS - default 0x80000000 - -config DCCM_SIZE - default 128 - config CACHE_FLUSHING def_bool y diff --git a/arch/arc/soc/em7d/dts.fixup b/arch/arc/soc/em7d/dts.fixup new file mode 100644 index 0000000000..e61cb01e5e --- /dev/null +++ b/arch/arc/soc/em7d/dts.fixup @@ -0,0 +1,9 @@ +/* SoC level DTS fixup file */ + +#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS +#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10) + +#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS +#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) + +/* End of SoC Level DTS fixup file */ diff --git a/arch/arc/soc/em7d/linker.ld b/arch/arc/soc/em7d/linker.ld index 3a7cdb3c5b..e045de9af1 100644 --- a/arch/arc/soc/em7d/linker.ld +++ b/arch/arc/soc/em7d/linker.ld @@ -29,4 +29,5 @@ #define DCCM_START CONFIG_DCCM_BASE_ADDRESS #define DCCM_SIZE CONFIG_DCCM_SIZE +#include #include diff --git a/arch/arc/soc/em9d/Kconfig.defconfig b/arch/arc/soc/em9d/Kconfig.defconfig index 2dc116de4f..5756430ab4 100644 --- a/arch/arc/soc/em9d/Kconfig.defconfig +++ b/arch/arc/soc/em9d/Kconfig.defconfig @@ -29,30 +29,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config HARVARD def_bool y -config FLASH_BASE_ADDRESS - default 0x00000000 - -config FLASH_SIZE - default 0 - # em9d has no FLASH so size is 0. - -config SRAM_BASE_ADDRESS - default 0x00000000 - -config SRAM_SIZE - default 0 - # em9d has no SRAM so size is 0. - -config ICCM_BASE_ADDRESS - default 0x00000000 - -config ICCM_SIZE - default 256 - -config DCCM_BASE_ADDRESS - default 0x80000000 - -config DCCM_SIZE - default 128 - endif #SOC_EM9D diff --git a/arch/arc/soc/em9d/dts.fixup b/arch/arc/soc/em9d/dts.fixup new file mode 100644 index 0000000000..cb1cd04fdd --- /dev/null +++ b/arch/arc/soc/em9d/dts.fixup @@ -0,0 +1,12 @@ +/* SoC level DTS fixup file */ + +#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS +#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10) + +#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS +#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) + +#define CONFIG_SRAM_SIZE 0 +#define CONFIG_SRAM_BASE_ADDRESS 0 + +/* End of SoC Level DTS fixup file */ diff --git a/arch/arc/soc/em9d/linker.ld b/arch/arc/soc/em9d/linker.ld index 04de903238..20c2ad02e0 100644 --- a/arch/arc/soc/em9d/linker.ld +++ b/arch/arc/soc/em9d/linker.ld @@ -26,5 +26,6 @@ #define DCCM_START CONFIG_DCCM_BASE_ADDRESS #define DCCM_SIZE CONFIG_DCCM_SIZE +#include #include diff --git a/boards/arc/em_starterkit/Kconfig.board b/boards/arc/em_starterkit/Kconfig.board index 5eaff7cb94..849f47bb7e 100644 --- a/boards/arc/em_starterkit/Kconfig.board +++ b/boards/arc/em_starterkit/Kconfig.board @@ -7,6 +7,7 @@ config BOARD_EM_STARTERKIT bool "ARC EM Starter Kit" depends on (SOC_EM7D || SOC_EM9D || SOC_EM11D) + select HAS_DTS help The DesignWare ARC EM Starter Kit board is a board that can host up to 3 different SOC FPGA bit files. diff --git a/boards/arc/em_starterkit/arc_mpu_regions.c b/boards/arc/em_starterkit/arc_mpu_regions.c index 46bb39edd3..e357c78e39 100644 --- a/boards/arc/em_starterkit/arc_mpu_regions.c +++ b/boards/arc/em_starterkit/arc_mpu_regions.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include #include diff --git a/boards/arc/em_starterkit/em_starterkit.dts b/boards/arc/em_starterkit/em_starterkit.dts new file mode 100644 index 0000000000..26b1f0cb03 --- /dev/null +++ b/boards/arc/em_starterkit/em_starterkit.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +#include + +/ { + model = "em_starterkit-em9d"; + compatible = "snps,em_starterkit-em9d", "snps,em_starterkit"; + + aliases { + uart_0 = &uart0; + uart_1 = &uart1; + uart_2 = &uart2; + }; + + chosen { + zephyr,console = &uart1; + }; +}; + +&uart1 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/arc/em_starterkit/em_starterkit_em11d.dts b/boards/arc/em_starterkit/em_starterkit_em11d.dts new file mode 100644 index 0000000000..661b5a4db2 --- /dev/null +++ b/boards/arc/em_starterkit/em_starterkit_em11d.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +#include + +/ { + model = "em_starterkit-em11d"; + compatible = "snps,em_starterkit-em11d", "snps,em_starterkit"; + + aliases { + uart_0 = &uart0; + uart_1 = &uart1; + uart_2 = &uart2; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + }; +}; + +&uart1 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.dts b/boards/arc/em_starterkit/em_starterkit_em7d.dts new file mode 100644 index 0000000000..48604a4086 --- /dev/null +++ b/boards/arc/em_starterkit/em_starterkit_em7d.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +#include + +/ { + model = "em_starterkit-em7"; + compatible = "snps,em_starterkit-em7d", "snps,em_starterkit"; + + aliases { + uart_0 = &uart0; + uart_1 = &uart1; + uart_2 = &uart2; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart1; + }; +}; + +&uart1 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22.dts b/boards/arc/em_starterkit/em_starterkit_em7d_v22.dts new file mode 100644 index 0000000000..4757e4562c --- /dev/null +++ b/boards/arc/em_starterkit/em_starterkit_em7d_v22.dts @@ -0,0 +1 @@ +#include "em_starterkit_em7d.dts" diff --git a/dts/arc/em11d.dtsi b/dts/arc/em11d.dtsi new file mode 100644 index 0000000000..f9489bcc07 --- /dev/null +++ b/dts/arc/em11d.dtsi @@ -0,0 +1,38 @@ +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,arcem11d"; + reg = <1>; + }; + + intc: arcv2-intc@0 { + compatible = "snps,arcv2-intc"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + iccm0: iccm@0 { + device_type = "memory"; + compatible = "arc,iccm"; + reg = <0x0 0x10000>; + }; + + sram0: memory@10000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x10000000 0x8000000>; + }; + + dccm0: dccm@80000000 { + device_type = "memory"; + compatible = "arc,dccm"; + reg = <0x80000000 0x10000>; + }; +}; diff --git a/dts/arc/em7d.dtsi b/dts/arc/em7d.dtsi new file mode 100644 index 0000000000..ce10d427a2 --- /dev/null +++ b/dts/arc/em7d.dtsi @@ -0,0 +1,38 @@ +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,arcem7d"; + reg = <1>; + }; + + intc: arcv2-intc@0 { + compatible = "snps,arcv2-intc"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + iccm0: iccm@0 { + device_type = "memory"; + compatible = "arc,iccm"; + reg = <0x0 0x40000>; + }; + + sram0: memory@10000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x10000000 0x8000000>; + }; + + dccm0: dccm@80000000 { + device_type = "memory"; + compatible = "arc,dccm"; + reg = <0x80000000 0x20000>; + }; +}; diff --git a/dts/arc/em9d.dtsi b/dts/arc/em9d.dtsi new file mode 100644 index 0000000000..72f76f0d66 --- /dev/null +++ b/dts/arc/em9d.dtsi @@ -0,0 +1,32 @@ +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,arcem9d"; + reg = <1>; + }; + + intc: arcv2-intc@0 { + compatible = "snps,arcv2-intc"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + iccm0: iccm@0 { + device_type = "memory"; + compatible = "arc,iccm"; + reg = <0x0 0x40000>; + }; + + dccm0: dccm@80000000 { + device_type = "memory"; + compatible = "arc,dccm"; + reg = <0x80000000 0x20000>; + }; +}; diff --git a/dts/arc/emsk.dtsi b/dts/arc/emsk.dtsi new file mode 100644 index 0000000000..38ceac4905 --- /dev/null +++ b/dts/arc/emsk.dtsi @@ -0,0 +1,63 @@ +#include "skeleton.dtsi" +#include + +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + i2c0: i2c@f0004000 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0004000 0x1000>; + label = "I2C_0"; + interrupts = <25 1>; + interrupt-parent = <&intc>; + }; + + i2c1: i2c@f0005000 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0005000 0x1000>; + label = "I2C_1"; + interrupts = <26 1>; + interrupt-parent = <&intc>; + }; + + uart0: uart@f0008000 { + compatible = "ns16550"; + reg = <0xf0008000 0x1000>; + label = "UART_0"; + interrupts = <29 1>; + interrupt-parent = <&intc>; + + status = "disabled"; + }; + + uart1: uart@f0009000 { + compatible = "ns16550"; + reg = <0xf0009000 0x1000>; + label = "UART_1"; + interrupts = <30 1>; + interrupt-parent = <&intc>; + + status = "disabled"; + }; + + uart2: uart@f000a000 { + compatible = "ns16550"; + reg = <0xf000a000 0x1000>; + label = "UART_2"; + interrupts = <31 1>; + interrupt-parent = <&intc>; + + status = "disabled"; + }; + }; +};