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drivers: serial: nrfx: Add support for UARTE2 and UARTE3

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Extend the uart_nrfx_uarte driver to support all UARTE instances
available on nRF9160.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2019-01-15 13:20:14 +01:00 committed by Carles Cufí
parent 8ab0a14170
commit 61fe47ad15
2 changed files with 160 additions and 1 deletions
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78
drivers/serial/Kconfig.nrfx
View file

@ -110,6 +110,84 @@ config UART_1_NRF_TX_BUFFER_SIZE
endif # UART_1_NRF_UARTE
# ----------------- port 2 -----------------
config UART_2_NRF_UARTE
bool "nRF UARTE 2"
depends on HAS_HW_NRF_UARTE2
select NRF_UARTE_PERIPHERAL
help
Enable nRF UART with EasyDMA on port 2.
if UART_2_NRF_UARTE
config UART_2_INTERRUPT_DRIVEN
bool "Enable interrupt support on port 2"
depends on UART_INTERRUPT_DRIVEN
default y
help
This option enables UART interrupt support on port 2.
config UART_2_NRF_PARITY_BIT
bool "Enable parity bit"
help
Enable parity bit.
config UART_2_NRF_FLOW_CONTROL
bool "Enable flow control"
help
Enable flow control. If selected, additionally two pins, RTS and CTS
have to be configured.
config UART_2_NRF_TX_BUFFER_SIZE
int "Size of RAM buffer"
range 1 65535
default 32
help
Size of the transmit buffer for API function: fifo_fill.
This value is limited by range of TXD.MAXCNT register for
particular SoC.
endif # UART_2_NRF_UARTE
# ----------------- port 3 -----------------
config UART_3_NRF_UARTE
bool "nRF UARTE 3"
depends on HAS_HW_NRF_UARTE3
select NRF_UARTE_PERIPHERAL
help
Enable nRF UART with EasyDMA on port 3.
if UART_3_NRF_UARTE
config UART_3_INTERRUPT_DRIVEN
bool "Enable interrupt support on port 3"
depends on UART_INTERRUPT_DRIVEN
default y
help
This option enables UART interrupt support on port 3.
config UART_3_NRF_PARITY_BIT
bool "Enable parity bit"
help
Enable parity bit.
config UART_3_NRF_FLOW_CONTROL
bool "Enable flow control"
help
Enable flow control. If selected, additionally two pins, RTS and CTS
have to be configured.
config UART_3_NRF_TX_BUFFER_SIZE
int "Size of RAM buffer"
range 1 65535
default 32
help
Size of the transmit buffer for API function: fifo_fill.
This value is limited by range of TXD.MAXCNT register for
particular SoC.
endif # UART_3_NRF_UARTE
config NRF_UART_PERIPHERAL
bool

83
drivers/serial/uart_nrfx_uarte.c
View file

@ -15,7 +15,11 @@
#if (defined(CONFIG_UART_0_NRF_UARTE) && \
defined(CONFIG_UART_0_INTERRUPT_DRIVEN)) || \
(defined(CONFIG_UART_1_NRF_UARTE) && \
defined(CONFIG_UART_1_INTERRUPT_DRIVEN))
defined(CONFIG_UART_1_INTERRUPT_DRIVEN)) || \
(defined(CONFIG_UART_2_NRF_UARTE) && \
defined(CONFIG_UART_2_INTERRUPT_DRIVEN)) || \
(defined(CONFIG_UART_3_NRF_UARTE) && \
defined(CONFIG_UART_3_INTERRUPT_DRIVEN))
#define UARTE_INTERRUPT_DRIVEN (1u)
#endif
@ -728,3 +732,80 @@ static int uarte_instance_init(struct device *dev,
UART_NRF_UARTE_DEVICE(1);
#endif /* CONFIG_UART_1_NRF_UARTE */
#ifdef CONFIG_UART_2_NRF_UARTE
#ifdef CONFIG_UART_2_INTERRUPT_DRIVEN
#define UARTE_2_INTERRUPT_DRIVEN (1u)
#define UARTE_2_INTERRUPTS_INIT() UARTE_NRF_IRQ_ENABLED(2)
#define UARTE_2_CREATE_TX_BUFF UARTE_TX_BUFFER_INIT(2)
#define UARTE_2_DATA_INIT UARTE_DATA_INT(2)
#define UARTE_2_CONFIG_INIT UARTE_CONFIG_INT(2)
#else
#define UARTE_2_INTERRUPT_DRIVEN (0u)
#define UARTE_2_INTERRUPTS_INIT()
#define UARTE_2_CREATE_TX_BUFF
#define UARTE_2_DATA_INIT
#define UARTE_2_CONFIG_INIT
#endif /* CONFIG_UART_2_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_2_NRF_FLOW_CONTROL
#define UARTE_2_NRF_HWFC_CONFIG NRF_UARTE_HWFC_ENABLED
#else
#define UARTE_2_NRF_HWFC_CONFIG NRF_UARTE_HWFC_DISABLED
#endif /* CONFIG_UART_2_NRF_FLOW_CONTROL */
#if defined(DT_NORDIC_NRF_UARTE_UART_2_RTS_PIN) && \
defined(DT_NORDIC_NRF_UARTE_UART_2_CTS_PIN)
#define UARTE_2_NRF_RTS_CTS_PINS UARTE_NRF_RTS_CTS_SET(2)
#define UARTE_2_CONFIG_RTS_CTS .rts_cts_pins_set = true
#else
#define UARTE_2_NRF_RTS_CTS_PINS UARTE_NRF_RTS_CTS_NOT_SET
#define UARTE_2_CONFIG_RTS_CTS .rts_cts_pins_set = false
#endif
#ifdef CONFIG_UART_2_NRF_PARITY_BIT
#define UARTE_2_NRF_PARITY_BIT NRF_UARTE_PARITY_INCLUDED
#else
#define UARTE_2_NRF_PARITY_BIT NRF_UARTE_PARITY_EXCLUDED
#endif /* CONFIG_UART_2_NRF_PARITY_BIT */
UART_NRF_UARTE_DEVICE(2);
#endif /* CONFIG_UART_2_NRF_UARTE */
#ifdef CONFIG_UART_3_NRF_UARTE
#ifdef CONFIG_UART_3_INTERRUPT_DRIVEN
#define UARTE_3_INTERRUPT_DRIVEN (1u)
#define UARTE_3_INTERRUPTS_INIT() UARTE_NRF_IRQ_ENABLED(3)
#define UARTE_3_CREATE_TX_BUFF UARTE_TX_BUFFER_INIT(3)
#define UARTE_3_DATA_INIT UARTE_DATA_INT(3)
#define UARTE_3_CONFIG_INIT UARTE_CONFIG_INT(3)
#else
#define UARTE_3_INTERRUPT_DRIVEN (0u)
#define UARTE_3_INTERRUPTS_INIT()
#define UARTE_3_CREATE_TX_BUFF
#define UARTE_3_DATA_INIT
#define UARTE_3_CONFIG_INIT
#endif /* CONFIG_UART_3_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_3_NRF_FLOW_CONTROL
#define UARTE_3_NRF_HWFC_CONFIG NRF_UARTE_HWFC_ENABLED
#else
#define UARTE_3_NRF_HWFC_CONFIG NRF_UARTE_HWFC_DISABLED
#endif /* CONFIG_UART_3_NRF_FLOW_CONTROL */
#if defined(DT_NORDIC_NRF_UARTE_UART_3_RTS_PIN) && \
defined(DT_NORDIC_NRF_UARTE_UART_3_CTS_PIN)
#define UARTE_3_NRF_RTS_CTS_PINS UARTE_NRF_RTS_CTS_SET(3)
#define UARTE_3_CONFIG_RTS_CTS .rts_cts_pins_set = true
#else
#define UARTE_3_NRF_RTS_CTS_PINS UARTE_NRF_RTS_CTS_NOT_SET
#define UARTE_3_CONFIG_RTS_CTS .rts_cts_pins_set = false
#endif
#ifdef CONFIG_UART_3_NRF_PARITY_BIT
#define UARTE_3_NRF_PARITY_BIT NRF_UARTE_PARITY_INCLUDED
#else
#define UARTE_3_NRF_PARITY_BIT NRF_UARTE_PARITY_EXCLUDED
#endif /* CONFIG_UART_3_NRF_PARITY_BIT */
UART_NRF_UARTE_DEVICE(3);
#endif /* CONFIG_UART_3_NRF_UARTE */