diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
index a9a70d64ba..d9595311a9 100644
--- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
@@ -110,6 +110,17 @@
 	};
 
 	soc {
+
+		lsbpm: lsbpm@71d80 {
+			compatible = "intel,adsp-lsbpm";
+			reg = <0x71d80 0x0008>;
+		};
+
+		hsbpm: hsbpm@17a800 {
+			compatible = "intel,adsp-hsbpm";
+			reg = <0x17a800 0x0008>;
+		};
+
 		core_intc: core_intc@0 {
 			compatible = "cdns,xtensa-core-intc";
 			reg = <0x00 0x400>;
diff --git a/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h
index 56e78cdca5..e0a7175aad 100644
--- a/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h
+++ b/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_memory.h
@@ -161,17 +161,17 @@ struct ace_lpsram_regs {
 #endif
 
 /* These registers are for the L2 HP SRAM bank power management control and status.*/
-#define L2HSBPM_REG					0x17A800
-#define L2HSBPM_REG_SIZE			0x0008
+#define L2_HSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(hsbpm)))
+#define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm)))
 
 #define HPSRAM_REGS(block_idx)		((volatile struct ace_hpsram_regs *const) \
-	(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))
+	(L2_HSBPM_BASE + L2_HSBPM_SIZE * (block_idx)))
 
 /* These registers are for the L2 LP SRAM bank power management control and status.*/
-#define L2LSBPM_REG				0x71D80
-#define L2LSBPM_REG_SIZE			0x0008
+#define L2_LSBPM_BASE (DT_REG_ADDR(DT_NODELABEL(lsbpm)))
+#define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm)))
 
 #define LPSRAM_REGS(block_idx)		((volatile struct ace_lpsram_regs *const) \
-	(L2LSBPM_REG + L2LSBPM_REG_SIZE * (block_idx)))
+	(L2_LSBPM_BASE + L2_LSBPM_SIZE * (block_idx)))
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */