drivers: flash for the stm32l5x or stm32u5 serie with max 2MB
Adds the stm32u5 flash controller driver for this serie to the existing stm32l5 flash driver part Only 1 or 2 MB devices exist today (4MB is possible in the future). This flash controller driver is adapted from the flash_stm32l5.c Signed-off-by: Francois Ramu <francois.ramu@st.com>
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269adf5ca8
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623b0418b6
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@ -48,11 +48,12 @@ if(CONFIG_SOC_FLASH_STM32)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X flash_stm32f4x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X flash_stm32l5x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X flash_stm32l5_u5.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WLX flash_stm32l4x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X flash_stm32g4x.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32U5X flash_stm32l5_u5.c)
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endif()
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endif()
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_DOMAIN flash_stm32l5
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#define LOG_DOMAIN flash_stm32l5_u5
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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@ -15,18 +15,24 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include <drivers/flash.h>
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#include <init.h>
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#include <soc.h>
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#include <stm32l5xx_ll_icache.h>
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#include <stm32_ll_icache.h>
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#include <stm32_ll_system.h>
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#include "flash_stm32.h"
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#define STM32L5_SERIES_MAX_FLASH 512
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#define BANK2_OFFSET (KB(STM32L5_SERIES_MAX_FLASH) / 2)
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#if defined(CONFIG_SOC_SERIES_STM32L5X)
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#define STM32_SERIES_MAX_FLASH 512
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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/* at this time stm32u5 mcus have 1MB (stm32u575) or 2MB (stm32u585) */
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#define STM32_SERIES_MAX_FLASH 2048
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#endif
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#define BANK2_OFFSET (KB(STM32_SERIES_MAX_FLASH) / 2)
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#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
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#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
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static int stm32l5x_icache_disable(void)
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static int stm32_icache_disable(void)
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{
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int status = 0;
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uint32_t tickstart;
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@ -59,7 +65,7 @@ static int stm32l5x_icache_disable(void)
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return status;
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}
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static void stm32l5x_icache_enable(void)
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static void stm32_icache_enable(void)
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{
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LOG_DBG("I-cache Enable");
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LL_ICACHE_Enable();
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@ -117,7 +123,7 @@ bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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if (((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) &&
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(CONFIG_FLASH_SIZE < STM32L5_SERIES_MAX_FLASH)) {
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(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
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/*
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* In case of bank1/2 discontinuity, the range should not
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* start before bank2 and end beyond bank1 at the same time.
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@ -270,7 +276,7 @@ int flash_stm32_block_erase_loop(const struct device *dev,
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* i-cache is disabled. A write to flash performed without
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* disabling i-cache will set ERRF error flag in SR register.
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*/
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rc = stm32l5x_icache_disable();
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rc = stm32_icache_disable();
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if (rc != 0) {
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return rc;
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}
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@ -292,7 +298,7 @@ int flash_stm32_block_erase_loop(const struct device *dev,
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/* I-cache should be enabled only after the
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* invalidation is complete.
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*/
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stm32l5x_icache_enable();
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stm32_icache_enable();
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}
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return rc;
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@ -310,7 +316,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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* i-cache is disabled. A write to flash performed without
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* disabling i-cache will set ERRF error flag in SR register.
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*/
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rc = stm32l5x_icache_disable();
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rc = stm32_icache_disable();
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if (rc != 0) {
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return rc;
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}
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@ -332,7 +338,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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/* I-cache should be enabled only after the
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* invalidation is complete.
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*/
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stm32l5x_icache_enable();
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stm32_icache_enable();
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}
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return rc;
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@ -343,43 +349,51 @@ void flash_stm32_page_layout(const struct device *dev,
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size_t *layout_size)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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static struct flash_pages_layout stm32l5_flash_layout[3];
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static struct flash_pages_layout stm32_flash_layout[3];
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#define PAGES_PER_BANK ((FLASH_SIZE / FLASH_PAGE_SIZE) / 2)
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if (((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) &&
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(CONFIG_FLASH_SIZE < STM32L5_SERIES_MAX_FLASH)) {
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/* For stm32l552xx with 256 KB flash */
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if (stm32l5_flash_layout[0].pages_count == 0) {
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(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
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/*
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* For stm32l552xx with 256 KB flash
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* or For stm32u57x with 1MB flash
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*/
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if (stm32_flash_layout[0].pages_count == 0) {
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/* Bank1 */
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stm32l5_flash_layout[0].pages_count = PAGES_PER_BANK;
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stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
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stm32_flash_layout[0].pages_count = PAGES_PER_BANK;
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stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
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/* Dummy page corresponding to discontinuity between
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* bank 1/2
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*/
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stm32l5_flash_layout[1].pages_count = 1;
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stm32l5_flash_layout[1].pages_size = BANK2_OFFSET
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stm32_flash_layout[1].pages_count = 1;
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stm32_flash_layout[1].pages_size = BANK2_OFFSET
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- (PAGES_PER_BANK * FLASH_PAGE_SIZE);
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/* Bank2 */
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stm32l5_flash_layout[2].pages_count = PAGES_PER_BANK;
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stm32l5_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
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stm32_flash_layout[2].pages_count = PAGES_PER_BANK;
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stm32_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
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}
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} else {
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/* For stm32l562xx & stm32l552xx with 512 KB flash */
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/*
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* For stm32l562xx & stm32l552xx with 512 KB flash
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* or For stm32u58x with 2MB flash
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*/
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if (stm32l5_flash_layout[0].pages_count == 0) {
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if (stm32_flash_layout[0].pages_count == 0) {
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if ((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) {
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/* flash with dualbank has 2k pages */
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stm32l5_flash_layout[0].pages_count = FLASH_PAGE_NB;
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stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
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stm32_flash_layout[0].pages_count = FLASH_PAGE_NB;
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stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
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#if defined(CONFIG_SOC_SERIES_STM32L5X)
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} else {
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/* flash without dualbank has 4k pages */
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stm32l5_flash_layout[0].pages_count = FLASH_PAGE_NB_128_BITS;
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stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE_128_BITS;
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stm32_flash_layout[0].pages_count = FLASH_PAGE_NB_128_BITS;
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stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE_128_BITS;
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#endif /* CONFIG_SOC_SERIES_STM32L5X */
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}
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}
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}
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*layout = stm32l5_flash_layout;
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*layout_size = ARRAY_SIZE(stm32l5_flash_layout);
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*layout = stm32_flash_layout;
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*layout_size = ARRAY_SIZE(stm32_flash_layout);
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}
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