drivers: flash for the stm32l5x or stm32u5 serie with max 2MB

Adds the stm32u5 flash controller driver for this serie
to the existing stm32l5 flash driver part
Only 1 or 2 MB devices exist today (4MB is possible in the future).
This flash controller driver is adapted from the flash_stm32l5.c

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-02-04 12:23:58 +01:00 committed by Marti Bolivar
parent 269adf5ca8
commit 623b0418b6
2 changed files with 46 additions and 31 deletions

View file

@ -48,11 +48,12 @@ if(CONFIG_SOC_FLASH_STM32)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X flash_stm32f4x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X flash_stm32l5x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X flash_stm32l5_u5.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WLX flash_stm32l4x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X flash_stm32g4x.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32U5X flash_stm32l5_u5.c)
endif()
endif()

View file

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_DOMAIN flash_stm32l5
#define LOG_DOMAIN flash_stm32l5_u5
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
@ -15,18 +15,24 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <drivers/flash.h>
#include <init.h>
#include <soc.h>
#include <stm32l5xx_ll_icache.h>
#include <stm32_ll_icache.h>
#include <stm32_ll_system.h>
#include "flash_stm32.h"
#define STM32L5_SERIES_MAX_FLASH 512
#define BANK2_OFFSET (KB(STM32L5_SERIES_MAX_FLASH) / 2)
#if defined(CONFIG_SOC_SERIES_STM32L5X)
#define STM32_SERIES_MAX_FLASH 512
#elif defined(CONFIG_SOC_SERIES_STM32U5X)
/* at this time stm32u5 mcus have 1MB (stm32u575) or 2MB (stm32u585) */
#define STM32_SERIES_MAX_FLASH 2048
#endif
#define BANK2_OFFSET (KB(STM32_SERIES_MAX_FLASH) / 2)
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
static int stm32l5x_icache_disable(void)
static int stm32_icache_disable(void)
{
int status = 0;
uint32_t tickstart;
@ -59,7 +65,7 @@ static int stm32l5x_icache_disable(void)
return status;
}
static void stm32l5x_icache_enable(void)
static void stm32_icache_enable(void)
{
LOG_DBG("I-cache Enable");
LL_ICACHE_Enable();
@ -117,7 +123,7 @@ bool flash_stm32_valid_range(const struct device *dev, off_t offset,
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
if (((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) &&
(CONFIG_FLASH_SIZE < STM32L5_SERIES_MAX_FLASH)) {
(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
/*
* In case of bank1/2 discontinuity, the range should not
* start before bank2 and end beyond bank1 at the same time.
@ -270,7 +276,7 @@ int flash_stm32_block_erase_loop(const struct device *dev,
* i-cache is disabled. A write to flash performed without
* disabling i-cache will set ERRF error flag in SR register.
*/
rc = stm32l5x_icache_disable();
rc = stm32_icache_disable();
if (rc != 0) {
return rc;
}
@ -292,7 +298,7 @@ int flash_stm32_block_erase_loop(const struct device *dev,
/* I-cache should be enabled only after the
* invalidation is complete.
*/
stm32l5x_icache_enable();
stm32_icache_enable();
}
return rc;
@ -310,7 +316,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
* i-cache is disabled. A write to flash performed without
* disabling i-cache will set ERRF error flag in SR register.
*/
rc = stm32l5x_icache_disable();
rc = stm32_icache_disable();
if (rc != 0) {
return rc;
}
@ -332,7 +338,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
/* I-cache should be enabled only after the
* invalidation is complete.
*/
stm32l5x_icache_enable();
stm32_icache_enable();
}
return rc;
@ -343,43 +349,51 @@ void flash_stm32_page_layout(const struct device *dev,
size_t *layout_size)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
static struct flash_pages_layout stm32l5_flash_layout[3];
static struct flash_pages_layout stm32_flash_layout[3];
#define PAGES_PER_BANK ((FLASH_SIZE / FLASH_PAGE_SIZE) / 2)
if (((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) &&
(CONFIG_FLASH_SIZE < STM32L5_SERIES_MAX_FLASH)) {
/* For stm32l552xx with 256 KB flash */
if (stm32l5_flash_layout[0].pages_count == 0) {
(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
/*
* For stm32l552xx with 256 KB flash
* or For stm32u57x with 1MB flash
*/
if (stm32_flash_layout[0].pages_count == 0) {
/* Bank1 */
stm32l5_flash_layout[0].pages_count = PAGES_PER_BANK;
stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
stm32_flash_layout[0].pages_count = PAGES_PER_BANK;
stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
/* Dummy page corresponding to discontinuity between
* bank 1/2
*/
stm32l5_flash_layout[1].pages_count = 1;
stm32l5_flash_layout[1].pages_size = BANK2_OFFSET
stm32_flash_layout[1].pages_count = 1;
stm32_flash_layout[1].pages_size = BANK2_OFFSET
- (PAGES_PER_BANK * FLASH_PAGE_SIZE);
/* Bank2 */
stm32l5_flash_layout[2].pages_count = PAGES_PER_BANK;
stm32l5_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
stm32_flash_layout[2].pages_count = PAGES_PER_BANK;
stm32_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
}
} else {
/* For stm32l562xx & stm32l552xx with 512 KB flash */
/*
* For stm32l562xx & stm32l552xx with 512 KB flash
* or For stm32u58x with 2MB flash
*/
if (stm32l5_flash_layout[0].pages_count == 0) {
if (stm32_flash_layout[0].pages_count == 0) {
if ((regs->OPTR & FLASH_OPTR_DBANK) == FLASH_OPTR_DBANK) {
/* flash with dualbank has 2k pages */
stm32l5_flash_layout[0].pages_count = FLASH_PAGE_NB;
stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
stm32_flash_layout[0].pages_count = FLASH_PAGE_NB;
stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
#if defined(CONFIG_SOC_SERIES_STM32L5X)
} else {
/* flash without dualbank has 4k pages */
stm32l5_flash_layout[0].pages_count = FLASH_PAGE_NB_128_BITS;
stm32l5_flash_layout[0].pages_size = FLASH_PAGE_SIZE_128_BITS;
stm32_flash_layout[0].pages_count = FLASH_PAGE_NB_128_BITS;
stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE_128_BITS;
#endif /* CONFIG_SOC_SERIES_STM32L5X */
}
}
}
*layout = stm32l5_flash_layout;
*layout_size = ARRAY_SIZE(stm32l5_flash_layout);
*layout = stm32_flash_layout;
*layout_size = ARRAY_SIZE(stm32_flash_layout);
}