soc: arm64: add PFC files to Renesas r8a77961 Gen3 SoC
Add Pin Function Controller tables of registers and their bits for ARM64 Renesas R-Car family. With this changes we can use Renesas PFC driver for configuring bias and driving capabilities. Add only needed driver strength and bias pins to PFC, e.g. SDx and UART TX/RX pins. Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit is contained in:
Mykola Kvach
Carles Cufí
parent
38675f2b92
commit
634e73dd21
112
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h
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112
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h
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/*
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* Copyright (c) 2023 EPAM Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
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#include "pinctrl-rcar-common.h"
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/* Pins declaration */
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#define PIN_NONE -1
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#define PIN_SD0_CLK RCAR_GP_PIN(3, 0)
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#define PIN_SD0_CMD RCAR_GP_PIN(3, 1)
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#define PIN_SD0_DATA0 RCAR_GP_PIN(3, 2)
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#define PIN_SD0_DATA1 RCAR_GP_PIN(3, 3)
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#define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4)
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#define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5)
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#define PIN_SD0_CD RCAR_GP_PIN(3, 12)
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#define PIN_SD0_WP RCAR_GP_PIN(3, 13)
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#define PIN_SD1_CLK RCAR_GP_PIN(3, 6)
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#define PIN_SD1_CMD RCAR_GP_PIN(3, 7)
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/*
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* note: the next data pins shared with SD2,
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* and for SD2 they represent DATA4-DATA7
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*/
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#define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8)
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#define PIN_SD1_DATA1 RCAR_GP_PIN(3, 9)
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#define PIN_SD1_DATA2 RCAR_GP_PIN(3, 10)
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#define PIN_SD1_DATA3 RCAR_GP_PIN(3, 11)
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#define PIN_SD1_CD RCAR_GP_PIN(3, 14)
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#define PIN_SD1_WP RCAR_GP_PIN(3, 15)
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#define PIN_SD2_CLK RCAR_GP_PIN(4, 0)
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#define PIN_SD2_CMD RCAR_GP_PIN(4, 1)
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#define PIN_SD2_DATA0 RCAR_GP_PIN(4, 2)
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#define PIN_SD2_DATA1 RCAR_GP_PIN(4, 3)
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#define PIN_SD2_DATA2 RCAR_GP_PIN(4, 4)
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#define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5)
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#define PIN_SD2_DS RCAR_GP_PIN(4, 6)
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#define PIN_SD3_CLK RCAR_GP_PIN(4, 7)
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#define PIN_SD3_CMD RCAR_GP_PIN(4, 8)
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#define PIN_SD3_DATA0 RCAR_GP_PIN(4, 9)
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#define PIN_SD3_DATA1 RCAR_GP_PIN(4, 10)
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#define PIN_SD3_DATA2 RCAR_GP_PIN(4, 11)
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#define PIN_SD3_DATA3 RCAR_GP_PIN(4, 12)
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#define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13)
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#define PIN_SD3_DATA5 RCAR_GP_PIN(4, 14)
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#define PIN_SD3_DATA6 RCAR_GP_PIN(4, 15)
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#define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16)
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#define PIN_SD3_DS RCAR_GP_PIN(4, 17)
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#define PIN_TX2_A RCAR_GP_PIN(5, 10)
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#define PIN_RX2_A RCAR_GP_PIN(5, 11)
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/* Pinmux function declarations */
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#define FUNC_SD0_CLK IPSR(7, 12, 0)
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#define FUNC_SD0_CMD IPSR(7, 16, 0)
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#define FUNC_SD0_DAT0 IPSR(7, 20, 0)
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#define FUNC_SD0_DAT1 IPSR(7, 24, 0)
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#define FUNC_SD0_DAT2 IPSR(8, 0, 0)
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#define FUNC_SD0_DAT3 IPSR(8, 4, 0)
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#define FUNC_SD0_CD IPSR(11, 8, 0)
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#define FUNC_SD0_WP IPSR(11, 12, 0)
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#define FUNC_SD1_CLK IPSR(8, 8, 0)
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#define FUNC_SD1_CMD IPSR(8, 12, 0)
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#define FUNC_SD1_DAT0 IPSR(8, 16, 0)
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#define FUNC_SD1_DAT1 IPSR(8, 20, 0)
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#define FUNC_SD1_DAT2 IPSR(8, 24, 0)
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#define FUNC_SD1_DAT3 IPSR(8, 28, 0)
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#define FUNC_SD1_CD IPSR(11, 16, 0)
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#define FUNC_SD1_WP IPSR(11, 20, 0)
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#define FUNC_SD2_CLK IPSR(9, 0, 0)
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#define FUNC_SD2_CMD IPSR(9, 4, 0)
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#define FUNC_SD2_DAT0 IPSR(9, 8, 0)
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#define FUNC_SD2_DAT1 IPSR(9, 12, 0)
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#define FUNC_SD2_DAT2 IPSR(9, 16, 0)
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#define FUNC_SD2_DAT3 IPSR(9, 20, 0)
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#define FUNC_SD2_DAT4 IPSR(8, 16, 1)
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#define FUNC_SD2_DAT5 IPSR(8, 20, 1)
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#define FUNC_SD2_DAT6 IPSR(8, 24, 1)
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#define FUNC_SD2_DAT7 IPSR(8, 28, 1)
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#define FUNC_SD2_CD_A IPSR(10, 20, 1)
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#define FUNC_SD2_WP_A IPSR(10, 24, 1)
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#define FUNC_SD2_CD_B IPSR(13, 0, 3)
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#define FUNC_SD2_WP_B IPSR(13, 4, 3)
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#define FUNC_SD2_DS IPSR(9, 24, 0)
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#define FUNC_SD3_CLK IPSR(9, 28, 0)
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#define FUNC_SD3_CMD IPSR(10, 0, 0)
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#define FUNC_SD3_DAT0 IPSR(10, 4, 0)
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#define FUNC_SD3_DAT1 IPSR(10, 8, 0)
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#define FUNC_SD3_DAT2 IPSR(10, 12, 0)
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#define FUNC_SD3_DAT3 IPSR(10, 16, 0)
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#define FUNC_SD3_DAT4 IPSR(10, 20, 0)
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#define FUNC_SD3_DAT5 IPSR(10, 24, 0)
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#define FUNC_SD3_DAT6 IPSR(10, 28, 0)
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#define FUNC_SD3_DAT7 IPSR(11, 0, 0)
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#define FUNC_SD3_CD IPSR(10, 28, 1)
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#define FUNC_SD3_WP IPSR(11, 0, 1)
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#define FUNC_SD3_DS IPSR(11, 4, 0)
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#define FUNC_TX2_A IPSR(13, 0, 0)
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#define FUNC_RX2_A IPSR(13, 4, 0)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_ */
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@ -2,4 +2,5 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library_sources_ifdef(CONFIG_SOC_ARM64_R8A77951 pfc_r8a77951.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c)
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zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
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146
soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c
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146
soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c
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/*
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* Copyright (c) 2023 EPAM Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include "pinctrl_soc.h"
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
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const struct pfc_drive_reg pfc_drive_regs[] = {
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/* DRVCTRL13 */
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{ 0x0334, {
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{ RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
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{ RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
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{ RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
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{ RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
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{ RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
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{ RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
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} },
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/* DRVCTRL14 */
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{ 0x0338, {
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{ RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
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{ RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
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{ RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
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{ RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
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{ RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
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{ RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
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{ RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
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{ RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
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} },
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/* DRVCTRL15 */
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{ 0x033c, {
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{ RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
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{ RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
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{ RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
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{ RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
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{ RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
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{ RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
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{ RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
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{ RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
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} },
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/* DRVCTRL16 */
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{ 0x0340, {
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{ RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
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{ RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
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{ RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
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{ RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
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{ RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
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{ RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
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{ RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
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{ RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
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} },
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/* DRVCTRL17 */
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{ 0x0344, {
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{ RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
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{ RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
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{ RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
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{ RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
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{ RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
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{ RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
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{ RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
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{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
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} },
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/* DRVCTRL18 */
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{ 0x0348, {
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{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
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{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
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{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
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{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
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{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
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{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
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{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
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{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
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} },
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{ },
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};
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#define PFC_BIAS_REG(r1, r2) \
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.puen = r1, \
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.pud = r2, \
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.pins =
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const struct pfc_bias_reg pfc_bias_regs[] = {
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{ PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
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[0 ... 9] = PIN_NONE,
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[10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
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[11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
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[12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
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[13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
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[14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
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[15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
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[16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
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[17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
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[18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
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[19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
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[20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
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[21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
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[22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
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[23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
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[24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
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[25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
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[26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
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[27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
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[28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
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[29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
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[30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
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[31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
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} },
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{ PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
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[0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
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[1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
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[2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
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[3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
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[4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
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[5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
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[6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
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[7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
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[8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
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[9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
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[10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
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[11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
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[12] = RCAR_GP_PIN(5, 0), /* SCK0 */
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[13] = RCAR_GP_PIN(5, 1), /* RX0 */
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[14] = RCAR_GP_PIN(5, 2), /* TX0 */
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[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
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[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
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[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
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[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
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[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
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[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
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[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
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[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
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[23] = RCAR_GP_PIN(5, 11), /* RX2_A */
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[24 ... 31] = PIN_NONE,
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} },
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{ /* sentinel */ },
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};
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const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
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{
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return pfc_bias_regs;
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}
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const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
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{
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return pfc_drive_regs;
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}
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