arch: arc: split codes for SMP and codes for multicore
reported by #19599, this commit splits the codes for Zephyr SMP and codes for ARC mulicore. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
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@ -26,7 +26,7 @@ zephyr_library_sources_if_kconfig(irq_offload.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
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zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_connect.c)
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zephyr_library_sources_ifdef(CONFIG_SMP arc_smp.c)
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zephyr_library_sources_ifdef(CONFIG_ARC_CONNECT arc_smp.c)
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add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu)
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add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield)
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@ -6,7 +6,7 @@
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/**
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* @file
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* @brief codes required for ARC smp support
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* @brief codes required for ARC multicore and Zephyr smp support
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*
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*/
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#include <device.h>
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@ -23,6 +23,69 @@
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#define ARCV2_ICI_IRQ_PRIORITY 1
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volatile struct {
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void (*fn)(int, void*);
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void *arg;
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} arc_cpu_init[CONFIG_MP_NUM_CPUS];
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/*
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* arc_cpu_wake_flag is used to sync up master core and slave cores
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* Slave core will spin for arc_cpu_wake_flag until master core sets
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* it to the core id of slave core. Then, slave core clears it to notify
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* master core that it's waken
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*
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*/
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volatile u32_t arc_cpu_wake_flag;
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volatile char *arc_cpu_sp;
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/*
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* _curr_cpu is used to record the struct of _cpu_t of each cpu.
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* for efficient usage in assembly
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*/
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volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
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/* Called from Zephyr initialization */
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void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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void (*fn)(int, void *), void *arg)
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{
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_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
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arc_cpu_init[cpu_num].fn = fn;
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arc_cpu_init[cpu_num].arg = arg;
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/* set the initial sp of target sp through arc_cpu_sp
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* arc_cpu_wake_flag will protect arc_cpu_sp that
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* only one slave cpu can read it per time
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*/
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arc_cpu_sp = Z_THREAD_STACK_BUFFER(stack) + sz;
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arc_cpu_wake_flag = cpu_num;
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/* wait slave cpu to start */
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while (arc_cpu_wake_flag != 0) {
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;
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}
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}
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/* the C entry of slave cores */
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void z_arc_slave_start(int cpu_num)
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{
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void (*fn)(int, void*);
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#ifdef CONFIG_SMP
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z_icache_setup();
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z_irq_setup();
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z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
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irq_enable(IRQ_ICI);
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#endif
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/* call the function set by arch_start_cpu */
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fn = arc_cpu_init[cpu_num].fn;
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fn(cpu_num, arc_cpu_init[cpu_num].arg);
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}
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#ifdef CONFIG_SMP
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static void sched_ipi_handler(void *unused)
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{
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ARG_UNUSED(unused);
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@ -49,7 +112,6 @@ u64_t z_arc_smp_switch_in_isr(void)
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new_thread = (u32_t)z_get_next_ready_thread();
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if (new_thread != old_thread) {
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/* should check whether new_thread to relace old_thread */
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#ifdef CONFIG_TIMESLICING
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z_reset_time_slice();
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#endif
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@ -63,58 +125,6 @@ u64_t z_arc_smp_switch_in_isr(void)
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return ret;
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}
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volatile struct {
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void (*fn)(int, void*);
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void *arg;
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} arc_cpu_init[CONFIG_MP_NUM_CPUS];
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/*
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* arc_cpu_wake_flag is used to sync up master core and slave cores
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* Slave core will spin for arc_cpu_wake_flag until master core sets
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* it to the core id of slave core. Then, slave core clears it to notify
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* master core that it's waken
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*
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*/
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volatile u32_t arc_cpu_wake_flag;
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/*
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* _curr_cpu is used to record the struct of _cpu_t of each cpu.
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* for efficient usage in assembly
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*/
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volatile _cpu_t *_curr_cpu[CONFIG_MP_NUM_CPUS];
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/* Called from Zephyr initialization */
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void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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void (*fn)(int, void *), void *arg)
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{
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_curr_cpu[cpu_num] = &(_kernel.cpus[cpu_num]);
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arc_cpu_init[cpu_num].fn = fn;
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arc_cpu_init[cpu_num].arg = arg;
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arc_cpu_wake_flag = cpu_num;
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/* wait slave cpu to start */
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while (arc_cpu_wake_flag != 0) {
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;
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}
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}
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/* the C entry of slave cores */
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void z_arc_slave_start(int cpu_num)
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{
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void (*fn)(int, void*);
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z_icache_setup();
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z_irq_setup();
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z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
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irq_enable(IRQ_ICI);
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/* call the function set by arch_start_cpu */
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fn = arc_cpu_init[cpu_num].fn;
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fn(cpu_num, arc_cpu_init[cpu_num].arg);
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}
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/* arch implementation of sched_ipi */
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void arch_sched_ipi(void)
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{
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@ -170,3 +180,4 @@ static int arc_smp_init(struct device *dev)
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}
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SYS_INIT(arc_smp_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif
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@ -126,7 +126,7 @@ done_cache_invalidate:
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jl @_sys_resume_from_deep_sleep
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#endif
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#ifdef CONFIG_SMP
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#if CONFIG_MP_NUM_CPUS > 1
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_get_cpu_id r0
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breq r0, 0, _master_core_startup
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@ -137,12 +137,10 @@ _slave_core_wait:
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ld r1, [arc_cpu_wake_flag]
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brne r0, r1, _slave_core_wait
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ld sp, [arc_cpu_sp]
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/* signal master core that slave core runs */
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st 0, [arc_cpu_wake_flag]
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/* get sp set by master core */
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_get_curr_cpu_irq_stack sp
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#if defined(CONFIG_ARC_FIRQ_STACK)
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jl z_arc_firq_stack_set
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#endif
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