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drivers: rcar_cpg: do MMIO mapping inside driver

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Add MMIO mapping for Renesas CPG driver in order to avoid
mappings inside mmu_regions.c file. Remove MMU region for
Renesas CPG driver.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit is contained in:
Mykola Kvach 2023-04-05 01:17:42 +03:00 committed by Carles Cufí
parent f66212022d
commit 644b38a3b7
3 changed files with 14 additions and 14 deletions
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19
drivers/clock_control/clock_control_r8a7795_cpg_mssr.c
View file

@ -32,11 +32,11 @@ LOG_MODULE_DECLARE(clock_control_rcar);
#define R8A7795_CLK_CANFD_DIV_MASK 0x3f
struct r8a7795_cpg_mssr_config {
mm_reg_t base_address;
DEVICE_MMIO_ROM; /* Must be first */
};
struct r8a7795_cpg_mssr_data {
struct rcar_cpg_mssr_data cmn;
struct rcar_cpg_mssr_data cmn; /* Must be first */
};
/* NOTE: the array MUST be sorted by module field */
@ -72,7 +72,7 @@ static struct cpg_clk_info_table mod_props[] = {
RCAR_MOD_CLK_INFO_ITEM(314, R8A7795_CLK_SD0),
};
static int r8a7795_cpg_enable_disable_core(const struct r8a7795_cpg_mssr_config *cfg,
static int r8a7795_cpg_enable_disable_core(const struct device *dev,
struct cpg_clk_info_table *clk_info,
uint32_t enable)
{
@ -109,7 +109,7 @@ static int r8a7795_cpg_enable_disable_core(const struct r8a7795_cpg_mssr_config
}
if (!ret) {
rcar_cpg_write(cfg->base_address, clk_info->offset, reg);
rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg);
}
return ret;
}
@ -119,7 +119,6 @@ static int r8a7795_cpg_core_clock_endisable(const struct device *dev,
bool enable)
{
struct cpg_clk_info_table *clk_info;
const struct r8a7795_cpg_mssr_config *cfg = dev->config;
struct r8a7795_cpg_mssr_data *data = dev->data;
k_spinlock_key_t key;
int ret = 0;
@ -142,7 +141,7 @@ static int r8a7795_cpg_core_clock_endisable(const struct device *dev,
}
key = k_spin_lock(&data->cmn.lock);
r8a7795_cpg_enable_disable_core(cfg, clk_info, enable);
r8a7795_cpg_enable_disable_core(dev, clk_info, enable);
k_spin_unlock(&data->cmn.lock, key);
return ret;
@ -160,12 +159,11 @@ static int r8a7795_cpg_mssr_start_stop(const struct device *dev,
}
if (clk->domain == CPG_MOD) {
const struct r8a7795_cpg_mssr_config *config = dev->config;
struct r8a7795_cpg_mssr_data *data = dev->data;
k_spinlock_key_t key;
key = k_spin_lock(&data->cmn.lock);
ret = rcar_cpg_mstp_clock_endisable(config->base_address, clk->module, enable);
ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable);
k_spin_unlock(&data->cmn.lock, key);
} else if (clk->domain == CPG_CORE) {
ret = r8a7795_cpg_core_clock_endisable(dev, clk, enable);
@ -275,6 +273,8 @@ static int r8a7795_cpg_mssr_stop(const struct device *dev,
static int r8a7795_cpg_mssr_init(const struct device *dev)
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
rcar_cpg_build_clock_relationship(dev);
rcar_cpg_update_all_in_out_freq(dev);
return 0;
@ -289,11 +289,10 @@ static const struct clock_control_driver_api r8a7795_cpg_mssr_api = {
#define R8A7795_MSSR_INIT(inst) \
static struct r8a7795_cpg_mssr_config r8a7795_cpg_mssr##inst##_config = { \
.base_address = DT_INST_REG_ADDR(inst), \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \
}; \
\
static struct r8a7795_cpg_mssr_data r8a7795_cpg_mssr##inst##_data = { \
.cmn.base_addr = DT_INST_REG_ADDR(inst), \
.cmn.clk_info_table[CPG_CORE] = core_props, \
.cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
.cmn.clk_info_table[CPG_MOD] = mod_props, \

6
drivers/clock_control/clock_control_renesas_cpg_mssr.c
View file

@ -104,7 +104,7 @@ static uint32_t rcar_cpg_get_divider(const struct device *dev, struct cpg_clk_in
return 1;
}
reg_addr += data->base_addr;
reg_addr += DEVICE_MMIO_GET(dev);
reg_val = sys_read32(reg_addr);
if (data->get_div_helper) {
@ -313,10 +313,10 @@ int rcar_cpg_set_rate(const struct device *dev, clock_control_subsys_t sys,
ret = data->set_rate_helper(module, &divider, &div_mask);
if (!ret) {
int64_t out_rate;
uint32_t reg = sys_read32(clk_info->offset + data->base_addr);
uint32_t reg = sys_read32(clk_info->offset + DEVICE_MMIO_GET(dev));
reg &= ~div_mask;
rcar_cpg_write(data->base_addr, clk_info->offset, reg | divider);
rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg | divider);
clk_info->out_freq = RCAR_CPG_NONE;

3
drivers/clock_control/clock_control_renesas_cpg_mssr.h
View file

@ -10,6 +10,7 @@
#include <zephyr/spinlock.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/device_mmio.h>
#define CPG_NUM_DOMAINS 2
@ -31,7 +32,7 @@ struct cpg_clk_info_table {
};
struct rcar_cpg_mssr_data {
mem_addr_t base_addr;
DEVICE_MMIO_RAM; /* Must be first */
struct cpg_clk_info_table *clk_info_table[CPG_NUM_DOMAINS];
const uint32_t clk_info_table_size[CPG_NUM_DOMAINS];