diff --git a/boards/arm/s32z270dc2_r52/doc/index.rst b/boards/arm/s32z270dc2_r52/doc/index.rst index 934bfc9e7c..9ae309a33b 100644 --- a/boards/arm/s32z270dc2_r52/doc/index.rst +++ b/boards/arm/s32z270dc2_r52/doc/index.rst @@ -111,9 +111,8 @@ The Cortex-R52 cores are configured to run at 800 MHz. Serial Port =========== -The SoC has 12 LINFlexD instances that can be used in UART mode. Instance 0 -(defined as ``uart0`` in devicetree) is configured for the console and the -remaining are disabled and not configured. +The SoC has 12 LINFlexD instances that can be used in UART mode. The console can +be accessed by default on the USB micro-B connector `J119`. Watchdog ======== @@ -190,6 +189,14 @@ For example, you can build and run the :ref:`hello_world` sample for the board :board: s32z270dc2_rtu0_r52 :goals: build flash +In case you are using a newer PCB revision, you have to use an adapted board +definition as the default PCB revision is B. For example, if using revision D: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z270dc2_rtu0_r52@D + :goals: build flash + You should see the following message in the terminal: .. code-block:: console diff --git a/boards/arm/s32z270dc2_r52/revision.cmake b/boards/arm/s32z270dc2_r52/revision.cmake new file mode 100644 index 0000000000..87399444b7 --- /dev/null +++ b/boards/arm/s32z270dc2_r52/revision.cmake @@ -0,0 +1,8 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +board_check_revision( + FORMAT LETTER + DEFAULT_REVISION B + VALID_REVISIONS B D +) diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi similarity index 87% rename from boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi rename to boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi index 58d29e3f0d..482b43d4b7 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl.dtsi +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,17 @@ }; }; + uart9_default: uart9_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + emdio_default: emdio_default { group1 { pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi index 023c1586c1..eed395cce8 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi @@ -1,17 +1,11 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ #include -#include "s32z270dc2_r52-pinctrl.dtsi" - -&uart0 { - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; +#include "s32z270dc2_r52-pinctrl-common.dtsi" &spi0 { clock-frequency = <100000000>; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts index 5370a212fa..a865075808 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts @@ -14,8 +14,6 @@ chosen { zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; zephyr,canbus = &can0; }; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay new file mode 100644 index 0000000000..d11914ba2c --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay new file mode 100644 index 0000000000..1aa56e3ae2 --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + }; +}; + +&uart9 { + pinctrl-0 = <&uart9_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml new file mode 100644 index 0000000000..db8c9e6885 --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml @@ -0,0 +1,16 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z270dc2_rtu0_r52@D +name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay new file mode 100644 index 0000000000..d11914ba2c --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay new file mode 100644 index 0000000000..1aa56e3ae2 --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay @@ -0,0 +1,18 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &uart9; + zephyr,shell-uart = &uart9; + }; +}; + +&uart9 { + pinctrl-0 = <&uart9_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml new file mode 100644 index 0000000000..aeb1eac203 --- /dev/null +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml @@ -0,0 +1,16 @@ +# Copyright 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z270dc2_rtu1_r52@D +name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can