drivers: dma: stm32: refactor irq handling
- Remove the need for kmalloc - On hardware that supports it use 1 IRQ handler per stream to determine the stream ID, so the ISR does not have to loop over all ID's to see which one is active. On hardware (like STM32L0 and STM32F0) where up to 7 streams share 3 IRQ's use the loop to check which stream is active. Signed-off-by: Erwin Rol <erwin@erwinrol.com>
This commit is contained in:
Erwin Rol
Carles Cufí
parent
c8ae070de7
commit
67f68e68f1
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@ -6,7 +6,7 @@
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config DMA_STM32
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bool "Enable STM32 DMA driver"
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select DYNAMIC_INTERRUPTS
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select USE_STM32_LL_DMA
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depends on SOC_FAMILY_STM32
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help
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DMA driver for STM32 series SoCs.
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@ -16,14 +16,12 @@ if DMA_STM32
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config DMA_STM32_V1
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bool
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depends on SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
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select USE_STM32_LL_DMA
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help
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Enable DMA support on F2/F4/F7 series SoCs.
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config DMA_STM32_V2
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bool
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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select USE_STM32_LL_DMA
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help
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Enable DMA support on F0/F1/F3/L0/L4/WB series SoCs.
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@ -34,4 +32,11 @@ config DMAMUX_STM32
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help
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Enable DMAMUX support on L4R/WB series SoCs.
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config DMA_STM32_SHARED_IRQS
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bool
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default y
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32L0X
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help
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Enable shared IRQ support on devices where channels share 1 IRQ.
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endif # DMA_STM32
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@ -24,6 +24,30 @@
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#include <logging/log.h>
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LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL);
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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#define DMA_STM32_0_STREAM_COUNT 8
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#elif DT_INST_IRQ_HAS_IDX(0, 6)
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#define DMA_STM32_0_STREAM_COUNT 7
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#elif DT_INST_IRQ_HAS_IDX(0, 5)
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#define DMA_STM32_0_STREAM_COUNT 6
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#else
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#define DMA_STM32_0_STREAM_COUNT 5
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#endif
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#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay)
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#if DT_INST_IRQ_HAS_IDX(1, 7)
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#define DMA_STM32_1_STREAM_COUNT 8
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#elif DT_INST_IRQ_HAS_IDX(1, 6)
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#define DMA_STM32_1_STREAM_COUNT 7
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#elif DT_INST_IRQ_HAS_IDX(1, 5)
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#define DMA_STM32_1_STREAM_COUNT 6
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#else
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#define DMA_STM32_1_STREAM_COUNT 5
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#endif
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#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */
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static uint32_t table_m_size[] = {
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LL_DMA_MDATAALIGN_BYTE,
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LL_DMA_MDATAALIGN_HALFWORD,
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@ -54,31 +78,16 @@ static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id)
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stm32_dma_clear_stream_irq(dma, id);
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}
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static void dma_stm32_irq_handler(void *arg)
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static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)
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{
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const struct device *dev = arg;
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struct dma_stm32_data *data = dev->data;
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const struct dma_stm32_config *config = dev->config;
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DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
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struct dma_stm32_stream *stream;
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int id;
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uint32_t callback_arg;
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for (id = 0; id < data->max_streams; id++) {
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if (func_ll_is_active_tc[id](dma)) {
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break;
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}
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if (stm32_dma_is_irq_happened(dma, id)) {
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break;
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}
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}
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__ASSERT_NO_MSG(id < config->max_streams);
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if (id == data->max_streams) {
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LOG_ERR("Unknown interrupt happened.");
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return;
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}
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stream = &data->streams[id];
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stream = &config->streams[id];
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#ifdef CONFIG_DMAMUX_STM32
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callback_arg = stream->mux_channel;
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@ -93,26 +102,42 @@ static void dma_stm32_irq_handler(void *arg)
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/* the dma stream id is in range from STREAM_OFFSET..<dma-requests> */
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if (func_ll_is_active_tc[id](dma)) {
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func_ll_clear_tc[id](dma);
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#ifdef CONFIG_DMAMUX_STM32
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stream->busy = false;
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#endif
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stream->dma_callback(dev, stream->user_data, callback_arg, 0);
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} else if (func_ll_is_active_ht[id](dma)) {
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func_ll_clear_ht[id](dma);
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} else if (stm32_dma_is_unexpected_irq_happened(dma, id)) {
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LOG_ERR("Unexpected irq happened.");
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stream->dma_callback(dev, stream->user_data,
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callback_arg, -EIO);
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} else {
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LOG_ERR("Transfer Error.");
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dma_stm32_dump_stream_irq(dev, id);
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dma_stm32_clear_stream_irq(dev, id);
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stream->dma_callback(dev, stream->user_data,
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callback_arg, -EIO);
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}
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}
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#ifdef CONFIG_DMA_STM32_SHARED_IRQS
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static void dma_stm32_shared_irq_handler(const struct device *dev)
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{
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const struct dma_stm32_config *cfg = dev->config;
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DMA_TypeDef *dma = (DMA_TypeDef *)(cfg->base);
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uint32_t id = 0;
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for (id = 0; id < cfg->max_streams; ++id) {
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if (stm32_dma_is_irq_active(dma, id)) {
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dma_stm32_irq_handler(dev, id);
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}
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}
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}
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#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
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static int dma_stm32_width_config(struct dma_config *config,
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bool source_periph,
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DMA_TypeDef *dma,
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@ -224,13 +249,13 @@ static int dma_stm32_get_periph_increment(enum dma_addr_adj increment,
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return 0;
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}
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DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev, uint32_t id,
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DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev,
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uint32_t id,
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struct dma_config *config)
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{
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struct dma_stm32_data *data = dev->data;
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struct dma_stm32_stream *stream = &data->streams[id - STREAM_OFFSET];
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const struct dma_stm32_config *dev_config =
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dev->config;
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const struct dma_stm32_config *dev_config = dev->config;
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struct dma_stm32_stream *stream =
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&dev_config->streams[id - STREAM_OFFSET];
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DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base;
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LL_DMA_InitTypeDef DMA_InitStruct;
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uint32_t msize;
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@ -239,7 +264,7 @@ DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev, uint32_t
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/* give channel from index 0 */
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id = id - STREAM_OFFSET;
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if (id >= data->max_streams) {
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if (id >= dev_config->max_streams) {
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LOG_ERR("cannot configure the dma stream %d.", id);
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return -EINVAL;
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}
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@ -462,13 +487,12 @@ DMA_STM32_EXPORT_API int dma_stm32_reload(const struct device *dev, uint32_t id,
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{
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const struct dma_stm32_config *config = dev->config;
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DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
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struct dma_stm32_data *data = dev->data;
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struct dma_stm32_stream *stream = &data->streams[id - STREAM_OFFSET];
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struct dma_stm32_stream *stream = &config->streams[id - STREAM_OFFSET];
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/* give channel from index 0 */
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id = id - STREAM_OFFSET;
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if (id >= data->max_streams) {
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if (id >= config->max_streams) {
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return -EINVAL;
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}
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@ -505,13 +529,12 @@ DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id)
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{
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const struct dma_stm32_config *config = dev->config;
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DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
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struct dma_stm32_data *data = dev->data;
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/* give channel from index 0 */
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id = id - STREAM_OFFSET;
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/* Only M2P or M2M mode can be started manually. */
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if (id >= data->max_streams) {
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if (id >= config->max_streams) {
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return -EINVAL;
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}
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@ -524,16 +547,14 @@ DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id)
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DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id)
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{
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struct dma_stm32_data *data = dev->data;
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struct dma_stm32_stream *stream = &data->streams[id - STREAM_OFFSET];
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const struct dma_stm32_config *config =
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dev->config;
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const struct dma_stm32_config *config = dev->config;
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struct dma_stm32_stream *stream = &config->streams[id - STREAM_OFFSET];
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DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
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/* give channel from index 0 */
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id = id - STREAM_OFFSET;
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if (id >= data->max_streams) {
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if (id >= config->max_streams) {
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return -EINVAL;
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}
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@ -553,11 +574,8 @@ DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id)
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return 0;
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}
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struct k_mem_block block;
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static int dma_stm32_init(const struct device *dev)
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{
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struct dma_stm32_data *data = dev->data;
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const struct dma_stm32_config *config = dev->config;
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const struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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@ -570,25 +588,16 @@ static int dma_stm32_init(const struct device *dev)
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config->config_irq(dev);
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int size_stream =
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sizeof(struct dma_stm32_stream) * data->max_streams;
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data->streams = k_malloc(size_stream);
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if (!data->streams) {
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LOG_ERR("HEAP_MEM_POOL_SIZE is too small");
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return -ENOMEM;
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}
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memset(data->streams, 0, size_stream);
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#ifdef CONFIG_DMAMUX_STM32
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int offset = ((dev == device_get_binding((const char *)"DMA_1"))
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? 0 : data->max_streams);
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? 0 : config->max_streams);
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#endif /* CONFIG_DMAMUX_STM32 */
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for (int i = 0; i < data->max_streams; i++) {
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data->streams[i].busy = false;
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for (uint32_t i = 0; i < config->max_streams; i++) {
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config->streams[i].busy = false;
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#ifdef CONFIG_DMAMUX_STM32
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/* each further stream->mux_channel is fixed here */
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data->streams[i].mux_channel = i + offset;
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config->streams[i].mux_channel = i + offset;
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#endif /* CONFIG_DMAMUX_STM32 */
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}
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@ -600,16 +609,15 @@ static int dma_stm32_get_status(const struct device *dev, uint32_t id,
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{
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const struct dma_stm32_config *config = dev->config;
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DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
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struct dma_stm32_data *data = dev->data;
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struct dma_stm32_stream *stream;
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/* give channel from index 0 */
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id = id - STREAM_OFFSET;
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if (id >= data->max_streams) {
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if (id >= config->max_streams) {
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return -EINVAL;
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}
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stream = &data->streams[id];
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stream = &config->streams[id];
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stat->pending_length = LL_DMA_GetDataLength(dma, table_ll_stream[id]);
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stat->dir = stream->direction;
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stat->busy = stream->busy;
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@ -625,8 +633,9 @@ static const struct dma_driver_api dma_funcs = {
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.get_status = dma_stm32_get_status,
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};
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#define DMA_INIT(index) \
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static void dma_stm32_config_irq_##index(const struct device *dev); \
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#define DMA_STM32_INIT_DEV(index) \
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static struct dma_stm32_stream \
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dma_stm32_streams_##index[DMA_STM32_##index##_STREAM_COUNT]; \
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\
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const struct dma_stm32_config dma_stm32_config_##index = { \
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.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
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@ -634,84 +643,147 @@ const struct dma_stm32_config dma_stm32_config_##index = { \
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.config_irq = dma_stm32_config_irq_##index, \
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.base = DT_INST_REG_ADDR(index), \
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.support_m2m = DT_INST_PROP(index, st_mem2mem), \
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.max_streams = DMA_STM32_##index##_STREAM_COUNT, \
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.streams = dma_stm32_streams_##index, \
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}; \
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\
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static struct dma_stm32_data dma_stm32_data_##index = { \
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.max_streams = 0, \
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.streams = NULL, \
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}; \
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\
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DEVICE_AND_API_INIT(dma_##index, DT_INST_LABEL(index), \
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DEVICE_AND_API_INIT(dma_stm32_##index##_dev, DT_INST_LABEL(index), \
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&dma_stm32_init, \
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&dma_stm32_data_##index, &dma_stm32_config_##index, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&dma_funcs)
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#define irq_func(chan) \
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static void dma_stm32_irq_##chan(void *arg) \
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{ \
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dma_stm32_irq_handler(arg, chan); \
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}
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#ifdef CONFIG_DMA_STM32_SHARED_IRQS
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#define IRQ_INIT(dma, chan) \
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#define DMA_STM32_DEFINE_IRQ_HANDLER(dma, chan) /* nothing */
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#define DMA_STM32_IRQ_CONNECT(dma, chan) \
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do { \
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if (!irq_is_enabled(DT_INST_IRQ_BY_IDX(dma, chan, irq))) { \
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irq_connect_dynamic(DT_INST_IRQ_BY_IDX(dma, chan, irq), \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(dma, chan, irq), \
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DT_INST_IRQ_BY_IDX(dma, chan, priority), \
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(void (*)(const void *)) \
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dma_stm32_irq_handler, dev, 0); \
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dma_stm32_shared_irq_handler, \
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DEVICE_GET(dma_stm32_##dma##_dev), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \
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} \
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data->max_streams++; \
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} while (0)
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#else /* CONFIG_DMA_STM32_SHARED_IRQS */
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#define DMA_STM32_DEFINE_IRQ_HANDLER(dma, chan) \
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static void dma_stm32_irq_##dma##_##chan(const struct device *dev) \
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{ \
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dma_stm32_irq_handler(dev, chan); \
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}
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#define DMA_STM32_IRQ_CONNECT(dma, chan) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(dma, chan, irq), \
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DT_INST_IRQ_BY_IDX(dma, chan, priority), \
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dma_stm32_irq_##dma##_##chan, \
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DEVICE_GET(dma_stm32_##dma##_dev), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(dma, chan, irq)); \
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} while (0)
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#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
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#if DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay)
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DMA_INIT(0);
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static void dma_stm32_config_irq_0(const struct device *dev)
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{
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struct dma_stm32_data *data = dev->data;
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DEVICE_DECLARE(dma_stm32_0_dev);
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IRQ_INIT(0, 0);
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IRQ_INIT(0, 1);
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IRQ_INIT(0, 2);
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IRQ_INIT(0, 3);
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IRQ_INIT(0, 4);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 0);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 1);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 2);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 3);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 4);
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#if DT_INST_IRQ_HAS_IDX(0, 5)
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IRQ_INIT(0, 5);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 5);
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#if DT_INST_IRQ_HAS_IDX(0, 6)
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IRQ_INIT(0, 6);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 6);
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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IRQ_INIT(0, 7);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 7);
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#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
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|
||||
static void dma_stm32_config_irq_0(const struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
DMA_STM32_IRQ_CONNECT(0, 0);
|
||||
DMA_STM32_IRQ_CONNECT(0, 1);
|
||||
#ifndef CONFIG_DMA_STM32_SHARED_IRQS
|
||||
DMA_STM32_IRQ_CONNECT(0, 2);
|
||||
#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
|
||||
DMA_STM32_IRQ_CONNECT(0, 3);
|
||||
#ifndef CONFIG_DMA_STM32_SHARED_IRQS
|
||||
DMA_STM32_IRQ_CONNECT(0, 4);
|
||||
#if DT_INST_IRQ_HAS_IDX(0, 5)
|
||||
DMA_STM32_IRQ_CONNECT(0, 5);
|
||||
#if DT_INST_IRQ_HAS_IDX(0, 6)
|
||||
DMA_STM32_IRQ_CONNECT(0, 6);
|
||||
#if DT_INST_IRQ_HAS_IDX(0, 7)
|
||||
DMA_STM32_IRQ_CONNECT(0, 7);
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
|
||||
#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
|
||||
/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
|
||||
}
|
||||
|
||||
DMA_STM32_INIT_DEV(0);
|
||||
|
||||
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
|
||||
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay)
|
||||
DMA_INIT(1);
|
||||
|
||||
static void dma_stm32_config_irq_1(const struct device *dev)
|
||||
{
|
||||
struct dma_stm32_data *data = dev->data;
|
||||
DEVICE_DECLARE(dma_stm32_1_dev);
|
||||
|
||||
IRQ_INIT(1, 0);
|
||||
IRQ_INIT(1, 1);
|
||||
IRQ_INIT(1, 2);
|
||||
IRQ_INIT(1, 3);
|
||||
IRQ_INIT(1, 4);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 0);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 1);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 2);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 3);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 4);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 5)
|
||||
IRQ_INIT(1, 5);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 5);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 6)
|
||||
IRQ_INIT(1, 6);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 6);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 7)
|
||||
IRQ_INIT(1, 7);
|
||||
DMA_STM32_DEFINE_IRQ_HANDLER(1, 7);
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 5) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 6) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 7) */
|
||||
|
||||
static void dma_stm32_config_irq_1(const struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
DMA_STM32_IRQ_CONNECT(1, 0);
|
||||
DMA_STM32_IRQ_CONNECT(1, 1);
|
||||
#ifndef CONFIG_DMA_STM32_SHARED_IRQS
|
||||
DMA_STM32_IRQ_CONNECT(1, 2);
|
||||
#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
|
||||
DMA_STM32_IRQ_CONNECT(1, 3);
|
||||
#ifndef CONFIG_DMA_STM32_SHARED_IRQS
|
||||
DMA_STM32_IRQ_CONNECT(1, 4);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 5)
|
||||
DMA_STM32_IRQ_CONNECT(1, 5);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 6)
|
||||
DMA_STM32_IRQ_CONNECT(1, 6);
|
||||
#if DT_INST_IRQ_HAS_IDX(1, 7)
|
||||
DMA_STM32_IRQ_CONNECT(1, 7);
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 5) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 6) */
|
||||
#endif /* DT_INST_IRQ_HAS_IDX(1, 7) */
|
||||
#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
|
||||
/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
|
||||
}
|
||||
|
||||
DMA_STM32_INIT_DEV(1);
|
||||
|
||||
#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(1), okay) */
|
||||
|
|
|
|||
|
|
@ -24,8 +24,6 @@ struct dma_stm32_stream {
|
|||
};
|
||||
|
||||
struct dma_stm32_data {
|
||||
int max_streams;
|
||||
struct dma_stm32_stream *streams;
|
||||
};
|
||||
|
||||
struct dma_stm32_config {
|
||||
|
|
@ -33,6 +31,8 @@ struct dma_stm32_config {
|
|||
void (*config_irq)(const struct device *dev);
|
||||
bool support_m2m;
|
||||
uint32_t base;
|
||||
uint32_t max_streams;
|
||||
struct dma_stm32_stream *streams;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_DMA_STM32_V1
|
||||
|
|
@ -57,6 +57,8 @@ extern void (*func_ll_clear_gi[])(DMA_TypeDef *DMAx);
|
|||
extern uint32_t table_ll_channel[];
|
||||
#endif
|
||||
|
||||
bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id);
|
||||
|
||||
void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id);
|
||||
void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id);
|
||||
bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id);
|
||||
|
|
|
|||
|
|
@ -160,6 +160,45 @@ void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id)
|
|||
func_ll_is_active_fe[id](dma));
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_TC(dma, id) &&
|
||||
func_ll_is_active_tc[id[(dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_HT(dma, id) &&
|
||||
func_ll_is_active_ht[id](dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_te_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_TE(dma, id) &&
|
||||
func_ll_is_active_te[id](dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_dme_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_DME(dma, id) &&
|
||||
func_ll_is_active_dme[id](dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_fe_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_FE(dma, id) &&
|
||||
func_ll_is_active_fe[id](dma);
|
||||
}
|
||||
|
||||
bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return stm32_dma_is_tc_irq_active(dma, id) ||
|
||||
stm32_dma_is_ht_irq_active(dma, id) ||
|
||||
stm32_dma_is_te_irq_active(dma, id) ||
|
||||
stm32_dma_is_dme_irq_active(dma, id) ||
|
||||
stm32_dma_is_fe_irq_active(dma, id);
|
||||
}
|
||||
|
||||
void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
func_ll_clear_te[id](dma);
|
||||
|
|
|
|||
|
|
@ -179,6 +179,32 @@ void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id)
|
|||
func_ll_is_active_gi[id](dma));
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_TC(dma, id) &&
|
||||
func_ll_is_active_tc[id](dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_HT(dma, id) &&
|
||||
func_ll_is_active_ht[id](dma);
|
||||
}
|
||||
|
||||
static inline bool stm32_dma_is_te_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return LL_DMA_IsEnabledIT_TE(dma, id) &&
|
||||
func_ll_is_active_te[id](dma);
|
||||
}
|
||||
|
||||
bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
return stm32_dma_is_tc_irq_active(dma, id) ||
|
||||
stm32_dma_is_ht_irq_active(dma, id) ||
|
||||
stm32_dma_is_te_irq_active(dma, id) ||
|
||||
func_ll_is_active_gi[id](dma);
|
||||
}
|
||||
|
||||
void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id)
|
||||
{
|
||||
func_ll_clear_te[id](dma);
|
||||
|
|
|
|||
Loading…
Reference in a new issue