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intel_adsp: add a header for soc specific defines

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Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.

In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-12 18:20:39 -04:00
parent e328508a66
commit 680df57582
6 changed files with 57 additions and 1 deletions
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11
soc/xtensa/intel_adsp/ace_v1x/fw_defs.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ADSP_PLATFORM_DEFS_H
#define ADSP_PLATFORM_DEFS_H
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
#endif

11
soc/xtensa/intel_adsp/cavs_v15/fw_defs.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ADSP_PLATFORM_DEFS_H
#define ADSP_PLATFORM_DEFS_H
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif

11
soc/xtensa/intel_adsp/cavs_v18/fw_defs.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ADSP_PLATFORM_DEFS_H
#define ADSP_PLATFORM_DEFS_H
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif

11
soc/xtensa/intel_adsp/cavs_v20/fw_defs.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ADSP_PLATFORM_DEFS_H
#define ADSP_PLATFORM_DEFS_H
#define ADSP_L1_CACHE_PREFCTL_VALUE 0
#endif

11
soc/xtensa/intel_adsp/cavs_v25/fw_defs.h Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2022 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ADSP_PLATFORM_DEFS_H
#define ADSP_PLATFORM_DEFS_H
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
#endif

3
soc/xtensa/intel_adsp/common/include/cpu_init.h
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@ -6,6 +6,7 @@
#include <zephyr/arch/xtensa/cache.h>
#include <xtensa/config/core-isa.h>
#include <fw_defs.h>
#define CxL1CCAP (*(volatile uint32_t *)0x9F080080)
#define CxL1CCFG (*(volatile uint32_t *)0x9F080084)
@ -61,7 +62,7 @@ static ALWAYS_INLINE void cpu_early_init(void)
* SOF for now. If we care about prefetch priority tuning
* we're supposed to ask Cadence I guess.
*/
reg = IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V25) ? 0x1038 : 0;
reg = ADSP_L1_CACHE_PREFCTL_VALUE;
__asm__ volatile("wsr %0, PREFCTL; rsync" :: "r"(reg));
/* Finally we need to enable the cache in the Region