patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

drivers: adc: gd32: use reset API

Browse source 
Use the reset API to reset the peripheral state before initialization.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2022-08-23 00:24:40 +02:00 committed by Carles Cufí
parent 014d831d80
commit 6894a6c7ed
6 changed files with 18 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/adc/adc_gd32.c
View file

@ -9,6 +9,7 @@
#include <errno.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/devicetree.h>
#include <gd32_adc.h>
@ -101,6 +102,7 @@ struct adc_gd32_config {
#ifdef CONFIG_SOC_SERIES_GD32F3X0
uint32_t rcu_clock_source;
#endif
struct reset_dt_spec reset;
uint8_t channels;
const struct pinctrl_dev_config *pcfg;
uint8_t irq_num;
@ -348,6 +350,8 @@ static int adc_gd32_init(const struct device *dev)
rcu_periph_clock_enable(cfg->rcu_periph_clock);
(void)reset_line_toggle_dt(&cfg->reset);
#if defined(CONFIG_SOC_SERIES_GD32F403) || \
defined(CONFIG_SOC_SERIES_GD32VF103) || \
defined(CONFIG_SOC_SERIES_GD32F3X0)
@ -446,6 +450,7 @@ static void adc_gd32_global_irq_cfg(void)
const static struct adc_gd32_config adc_gd32_config_##n = { \
.reg = DT_INST_REG_ADDR(n), \
.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \
.reset = RESET_DT_SPEC_INST_GET(n), \
.channels = DT_INST_PROP(n, channels), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.irq_num = DT_INST_IRQN(n), \

1
dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
View file

@ -73,6 +73,7 @@
interrupts = <12 0>;
rcu-periph-clock = <0x609>;
rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
resets = <&rctl GD32_RESET_ADC>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;

3
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
View file

@ -134,6 +134,7 @@
reg = <0x40012400 0x400>;
interrupts = <18 0>;
rcu-periph-clock = <0x609>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
@ -144,6 +145,7 @@
reg = <0x40012800 0x400>;
interrupts = <18 0>;
rcu-periph-clock = <0x60A>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
@ -154,6 +156,7 @@
reg = <0x40013c00 0x400>;
interrupts = <47 0>;
rcu-periph-clock = <0x60F>;
resets = <&rctl GD32_RESET_ADC2>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;

3
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
View file

@ -203,6 +203,7 @@
reg = <0x40012000 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x1108>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
@ -213,6 +214,7 @@
reg = <0x40012100 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x1109>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
@ -223,6 +225,7 @@
reg = <0x40012200 0x100>;
interrupts = <18 0>;
rcu-periph-clock = <0x110A>;
resets = <&rctl GD32_RESET_ADC2>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;

5
dts/bindings/adc/gd,gd32-adc.yaml
View file

@ -16,12 +16,15 @@ description: GigaDevice GD32 ADC
compatible: "gd,gd32-adc"
include: [adc-controller.yaml, pinctrl-device.yaml]
include: [adc-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
properties:
reg:
required: true
resets:
required: true
rcu-periph-clock:
type: int
description: Reset Control Unit Peripheral Clock ID

2
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -109,6 +109,7 @@
reg = <0x40012400 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x609>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
@ -119,6 +120,7 @@
reg = <0x40012800 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x60A>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;