dts: arm: cypress: Introduce PSoC-6 pinctrl

Introduce PSoC-6 pinctrl infraestructure and definitions.  This add
files to handle devicetree entries and following modifications:

 - add pinctrl bindings
 - update gpio bindings with pin-cells
 - add pinctrl node and move gpio nodes inside
 - declare pinctrl for current uart entries

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>

CODEOWNERS

@@ -318,6 +318,7 @@
 /dts/arm/atmel/samv71*                    @nandojve
 /dts/arm/atmel/                           @galak
 /dts/arm/broadcom/                        @sbranden
+/dts/arm/cypress/                         @nandojve
 /dts/arm/infineon/                        @parthitce
 /dts/arm/qemu-virt/                       @carlocaione
 /dts/arm/quicklogic/                      @wtatarski @kowalewskijan @kgugala
@@ -358,6 +359,7 @@
 /dts/bindings/serial/ns16550.yaml         @dcpleung @nashif
 /dts/bindings/wifi/*esp.yaml              @mniestroj
 /dts/bindings/*/*npcx*                    @MulinChao @WealianLiao @ChiHuaL
+/dts/bindings/*/*psoc6*                   @nandojve
 /dts/bindings/*/nordic*                   @anangl
 /dts/bindings/*/nxp*                      @MaureenHelm
 /dts/bindings/*/openisa*                  @MaureenHelm

dts/arm/cypress/pinctrl_cypress_psoc6.h

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ * Copyright (c) 2021 ATL Electronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef PINCTRL_CYPRESS_PSOC6_H_
+#define PINCTRL_CYPRESS_PSOC6_H_
+
+#include <dt-bindings/dt-util.h>
+
+/**
+ * Functions are defined using HSIOM SEL
+ */
+
+#define HSIOM_SEL_gpio          0
+#define HSIOM_SEL_gpio_dsi      1
+#define HSIOM_SEL_dsi_dsi       2
+#define HSIOM_SEL_dsi_gpio      3
+#define HSIOM_SEL_amuxa         4
+#define HSIOM_SEL_amuxb         5
+#define HSIOM_SEL_amuxa_dsi     6
+#define HSIOM_SEL_amuxb_dsi     7
+#define HSIOM_SEL_act_0         8
+#define HSIOM_SEL_act_1         9
+#define HSIOM_SEL_act_2        10
+#define HSIOM_SEL_act_3        11
+#define HSIOM_SEL_ds_0         12
+#define HSIOM_SEL_ds_1         13
+#define HSIOM_SEL_ds_2         14
+#define HSIOM_SEL_ds_3         15
+#define HSIOM_SEL_act_4        16
+#define HSIOM_SEL_act_5        17
+#define HSIOM_SEL_act_6        18
+#define HSIOM_SEL_act_7        19
+#define HSIOM_SEL_act_8        20
+#define HSIOM_SEL_act_9        21
+#define HSIOM_SEL_act_10       22
+#define HSIOM_SEL_act_11       23
+#define HSIOM_SEL_act_12       24
+#define HSIOM_SEL_act_13       25
+#define HSIOM_SEL_act_14       26
+#define HSIOM_SEL_act_15       27
+#define HSIOM_SEL_ds_4         28
+#define HSIOM_SEL_ds_5         29
+#define HSIOM_SEL_ds_6         30
+#define HSIOM_SEL_ds_7         31
+
+
+/* Create a pincfg device tree node:
+ *
+ * The node name and nodelabel will be of the form:
+ *
+ * NODE = p<port>_<pin>_<inst>_<signal>
+ *
+ * NODE: NODE {
+ *	cypress,pins = < &gpio_prt<port> <pin> HSIOM_SEL_<hsiom> >;
+ *	flags_1;
+ *	  ...
+ *	flags_N;
+ * }
+ *
+ * So for example:
+ *
+ * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6);
+ *
+ * Will become:
+ *
+ * p5_0_uart5_rx: p5_0_uart5_rx {
+ *    cypress,pins = <&gpio_prt5 0x0 0x12 >;
+ * }
+ *
+ * Flags are optional and should be pass one by one as arguments:
+ *
+ * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6, bias-pull-up, input-enable);
+ *
+ * Will become:
+ *
+ * p5_0_uart5_rx: p5_0_uart5_rx {
+ *    cypress,pins = <&gpio_prt5 0x0 0x12 >;
+ *    bias-pull-up;
+ *    input-enable;
+ * }
+ *
+ * For the complete list of flags see cypress,psoc6-pinctrl.yaml
+ *
+ */
+
+#define DT_CYPRESS_HSIOM_FLAG(flag) flag;
+#define DT_CYPRESS_HSIOM_FLAGS(...) \
+	MACRO_MAP_CAT(DT_CYPRESS_HSIOM_FLAG __VA_OPT__(,) __VA_ARGS__)
+
+#define DT_CYPRESS_HSIOM(inst, signal, port, pin, hsiom, ...) \
+	p##port##_##pin##_##inst##_##signal: \
+	p##port##_##pin##_##inst##_##signal { \
+	cypress,pins = < &gpio_prt##port pin HSIOM_SEL_##hsiom > ; \
+		DT_CYPRESS_HSIOM_FLAGS(__VA_ARGS__) \
+	}
+
+#endif /* PINCTRL_CYPRESS_PSOC6_H_ */

dts/arm/cypress/psoc6-pinctrl.dtsi

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "pinctrl_cypress_psoc6.h"
+
+/ {
+	soc {
+		pinctrl@40310000 {
+			/* instance, signal, port, pin, hsiom [, flag1, ... ] */
+			DT_CYPRESS_HSIOM(uart5,  rx,  5, 0, act_6, input-enable);
+			DT_CYPRESS_HSIOM(uart5,  tx,  5, 1, act_6, drive-push-pull);
+			DT_CYPRESS_HSIOM(uart6,  rx, 13, 0, act_6, input-enable);
+			DT_CYPRESS_HSIOM(uart6,  tx, 13, 1, act_6, drive-push-pull);
+		};
+	};
+};

dts/arm/cypress/psoc6.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, Cypress
+ * Copyright (c) 2020-2021, ATL Electronics
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +8,8 @@
 #include <mem.h>
 #include <dt-bindings/gpio/gpio.h>
 
+#include "psoc6-pinctrl.dtsi"
+
 / {
 	cpus {
 		#address-cells = <1>;
@@ -64,6 +67,12 @@
 	};
 
 	soc {
+		pinctrl@40310000 {
+			compatible = "cypress,psoc6-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x40310000 0x40310000 0x2024>;
+
 			hsiom: hsiom@40310000 {
 				compatible = "cypress,psoc6-hsiom";
 				reg = <0x40310000 0x2024>;
@@ -80,6 +89,7 @@
 				gpio-controller;
 				ngpios = <6>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt1: gpio@40320080 {
@@ -90,6 +100,7 @@
 				gpio-controller;
 				ngpios = <6>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt2: gpio@40320100 {
@@ -100,6 +111,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt3: gpio@40320180 {
@@ -110,6 +122,7 @@
 				gpio-controller;
 				ngpios = <6>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt4: gpio@40320200 {
@@ -120,6 +133,7 @@
 				gpio-controller;
 				ngpios = <4>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt5: gpio@40320280 {
@@ -130,6 +144,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt6: gpio@40320300 {
@@ -140,6 +155,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt7: gpio@40320380 {
@@ -150,6 +166,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt8: gpio@40320400 {
@@ -160,6 +177,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt9: gpio@40320480 {
@@ -170,6 +188,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt10: gpio@40320500 {
@@ -180,6 +199,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt11: gpio@40320580 {
@@ -190,6 +210,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt12: gpio@40320600 {
@@ -200,6 +221,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt13: gpio@40320680 {
@@ -210,6 +232,7 @@
 				gpio-controller;
 				ngpios = <8>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
 			gpio_prt14: gpio@40320700 {
@@ -220,8 +243,10 @@
 				gpio-controller;
 				ngpios = <2>;
 				#gpio-cells = <2>;
+				#cypress,pin-cells = <2>;
 				status = "disabled";
 			};
+		};
 
 		uart5: uart@40660000 {
 			compatible = "cypress,psoc6-uart";

dts/bindings/gpio/cypress,psoc6-gpio.yaml

@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ATL Electronics
+# Copyright (c) 2020-2021 ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
 description: Cypress GPIO PORT node
@@ -20,6 +20,16 @@ properties:
     "#gpio-cells":
       const: 2
 
+    "#cypress,pin-cells":
+      type: int
+      required: true
+      const: 2
+      description: Number of items to expect in a cypress,pins specifier
+
 gpio-cells:
   - pin
   - flags
+
+cypress,pin-cells:
+  - pin
+  - hsiom

dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2020, Linaro Limited
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress PSoC-6 Pinctrl container node
+
+  The Cypress PSoC-6 pins implements following pin configuration option:
+
+    * bias-pull-up
+    * bias-pull-down
+    * drive-open-drain
+    * drive-open-source
+    * drive-push-pull   (strong)
+    * input-enable      (input-buffer)
+
+  These options define devicetree flags that are converted to SoC flags at
+  CY_PSOC6_PIN_FLAGS().
+
+compatible: "cypress,psoc6-pinctrl"
+
+include: [base.yaml, pincfg-node.yaml]
+
+properties:
+    "#address-cells":
+      required: true
+      const: 1
+    "#size-cells":
+      required: true
+      const: 1
+
+child-binding:
+    description: cypress pins
+    properties:
+      "cypress,pins":
+        type: phandle-array