dts: arm: cypress: Introduce PSoC-6 pinctrl
Introduce PSoC-6 pinctrl infraestructure and definitions. This add files to handle devicetree entries and following modifications: - add pinctrl bindings - update gpio bindings with pin-cells - add pinctrl node and move gpio nodes inside - declare pinctrl for current uart entries Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This commit is contained in:
Gerson Fernando Budke
Kumar Gala
parent
90d0eb7947
commit
68dcac3be6
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@ -318,6 +318,7 @@
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/dts/arm/atmel/samv71* @nandojve
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/dts/arm/atmel/ @galak
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/dts/arm/broadcom/ @sbranden
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/dts/arm/cypress/ @nandojve
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/dts/arm/infineon/ @parthitce
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/dts/arm/qemu-virt/ @carlocaione
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/dts/arm/quicklogic/ @wtatarski @kowalewskijan @kgugala
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@ -358,6 +359,7 @@
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/dts/bindings/serial/ns16550.yaml @dcpleung @nashif
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/dts/bindings/wifi/*esp.yaml @mniestroj
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/dts/bindings/*/*npcx* @MulinChao @WealianLiao @ChiHuaL
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/dts/bindings/*/*psoc6* @nandojve
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/dts/bindings/*/nordic* @anangl
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/dts/bindings/*/nxp* @MaureenHelm
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/dts/bindings/*/openisa* @MaureenHelm
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100
dts/arm/cypress/pinctrl_cypress_psoc6.h
Normal file
100
dts/arm/cypress/pinctrl_cypress_psoc6.h
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@ -0,0 +1,100 @@
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/*
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* Copyright (c) 2020 Linaro Limited
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* Copyright (c) 2021 ATL Electronics
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef PINCTRL_CYPRESS_PSOC6_H_
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#define PINCTRL_CYPRESS_PSOC6_H_
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#include <dt-bindings/dt-util.h>
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/**
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* Functions are defined using HSIOM SEL
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*/
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#define HSIOM_SEL_gpio 0
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#define HSIOM_SEL_gpio_dsi 1
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#define HSIOM_SEL_dsi_dsi 2
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#define HSIOM_SEL_dsi_gpio 3
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#define HSIOM_SEL_amuxa 4
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#define HSIOM_SEL_amuxb 5
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#define HSIOM_SEL_amuxa_dsi 6
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#define HSIOM_SEL_amuxb_dsi 7
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#define HSIOM_SEL_act_0 8
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#define HSIOM_SEL_act_1 9
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#define HSIOM_SEL_act_2 10
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#define HSIOM_SEL_act_3 11
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#define HSIOM_SEL_ds_0 12
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#define HSIOM_SEL_ds_1 13
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#define HSIOM_SEL_ds_2 14
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#define HSIOM_SEL_ds_3 15
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#define HSIOM_SEL_act_4 16
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#define HSIOM_SEL_act_5 17
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#define HSIOM_SEL_act_6 18
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#define HSIOM_SEL_act_7 19
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#define HSIOM_SEL_act_8 20
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#define HSIOM_SEL_act_9 21
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#define HSIOM_SEL_act_10 22
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#define HSIOM_SEL_act_11 23
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#define HSIOM_SEL_act_12 24
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#define HSIOM_SEL_act_13 25
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#define HSIOM_SEL_act_14 26
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#define HSIOM_SEL_act_15 27
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#define HSIOM_SEL_ds_4 28
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#define HSIOM_SEL_ds_5 29
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#define HSIOM_SEL_ds_6 30
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#define HSIOM_SEL_ds_7 31
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/* Create a pincfg device tree node:
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*
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* The node name and nodelabel will be of the form:
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*
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* NODE = p<port>_<pin>_<inst>_<signal>
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*
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* NODE: NODE {
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* cypress,pins = < &gpio_prt<port> <pin> HSIOM_SEL_<hsiom> >;
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* flags_1;
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* ...
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* flags_N;
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* }
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*
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* So for example:
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*
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* DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6);
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*
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* Will become:
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*
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* p5_0_uart5_rx: p5_0_uart5_rx {
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* cypress,pins = <&gpio_prt5 0x0 0x12 >;
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* }
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*
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* Flags are optional and should be pass one by one as arguments:
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*
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* DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6, bias-pull-up, input-enable);
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*
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* Will become:
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*
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* p5_0_uart5_rx: p5_0_uart5_rx {
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* cypress,pins = <&gpio_prt5 0x0 0x12 >;
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* bias-pull-up;
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* input-enable;
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* }
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*
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* For the complete list of flags see cypress,psoc6-pinctrl.yaml
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*
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*/
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#define DT_CYPRESS_HSIOM_FLAG(flag) flag;
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#define DT_CYPRESS_HSIOM_FLAGS(...) \
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MACRO_MAP_CAT(DT_CYPRESS_HSIOM_FLAG __VA_OPT__(,) __VA_ARGS__)
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#define DT_CYPRESS_HSIOM(inst, signal, port, pin, hsiom, ...) \
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p##port##_##pin##_##inst##_##signal: \
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p##port##_##pin##_##inst##_##signal { \
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cypress,pins = < &gpio_prt##port pin HSIOM_SEL_##hsiom > ; \
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DT_CYPRESS_HSIOM_FLAGS(__VA_ARGS__) \
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}
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#endif /* PINCTRL_CYPRESS_PSOC6_H_ */
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19
dts/arm/cypress/psoc6-pinctrl.dtsi
Normal file
19
dts/arm/cypress/psoc6-pinctrl.dtsi
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2021 ATL Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "pinctrl_cypress_psoc6.h"
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/ {
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soc {
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pinctrl@40310000 {
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/* instance, signal, port, pin, hsiom [, flag1, ... ] */
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DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, input-enable);
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DT_CYPRESS_HSIOM(uart5, tx, 5, 1, act_6, drive-push-pull);
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DT_CYPRESS_HSIOM(uart6, rx, 13, 0, act_6, input-enable);
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DT_CYPRESS_HSIOM(uart6, tx, 13, 1, act_6, drive-push-pull);
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};
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};
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};
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018, Cypress
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* Copyright (c) 2020-2021, ATL Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,6 +8,8 @@
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#include <mem.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "psoc6-pinctrl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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@ -64,6 +67,12 @@
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};
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soc {
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pinctrl@40310000 {
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compatible = "cypress,psoc6-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x40310000 0x40310000 0x2024>;
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hsiom: hsiom@40310000 {
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compatible = "cypress,psoc6-hsiom";
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reg = <0x40310000 0x2024>;
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@ -80,6 +89,7 @@
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gpio-controller;
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ngpios = <6>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt1: gpio@40320080 {
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@ -90,6 +100,7 @@
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gpio-controller;
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ngpios = <6>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt2: gpio@40320100 {
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@ -100,6 +111,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt3: gpio@40320180 {
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@ -110,6 +122,7 @@
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gpio-controller;
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ngpios = <6>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt4: gpio@40320200 {
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@ -120,6 +133,7 @@
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gpio-controller;
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ngpios = <4>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt5: gpio@40320280 {
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@ -130,6 +144,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt6: gpio@40320300 {
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@ -140,6 +155,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt7: gpio@40320380 {
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt8: gpio@40320400 {
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@ -160,6 +177,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt9: gpio@40320480 {
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@ -170,6 +188,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt10: gpio@40320500 {
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@ -180,6 +199,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt11: gpio@40320580 {
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@ -190,6 +210,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt12: gpio@40320600 {
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt13: gpio@40320680 {
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@ -210,6 +232,7 @@
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gpio-controller;
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ngpios = <8>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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gpio_prt14: gpio@40320700 {
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gpio-controller;
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ngpios = <2>;
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#gpio-cells = <2>;
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#cypress,pin-cells = <2>;
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status = "disabled";
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};
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};
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uart5: uart@40660000 {
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compatible = "cypress,psoc6-uart";
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@ -1,4 +1,4 @@
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# Copyright (c) 2020 ATL Electronics
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# Copyright (c) 2020-2021 ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: Cypress GPIO PORT node
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@ -20,6 +20,16 @@ properties:
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"#gpio-cells":
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const: 2
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"#cypress,pin-cells":
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type: int
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required: true
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const: 2
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description: Number of items to expect in a cypress,pins specifier
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gpio-cells:
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- pin
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- flags
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cypress,pin-cells:
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- pin
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- hsiom
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36
dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml
Normal file
36
dts/bindings/pinctrl/cypress,psoc6-pinctrl.yaml
Normal file
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@ -0,0 +1,36 @@
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# Copyright (c) 2020, Linaro Limited
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# Copyright (c) 2021, ATL Electronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Cypress PSoC-6 Pinctrl container node
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The Cypress PSoC-6 pins implements following pin configuration option:
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* bias-pull-up
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* bias-pull-down
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* drive-open-drain
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* drive-open-source
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* drive-push-pull (strong)
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* input-enable (input-buffer)
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These options define devicetree flags that are converted to SoC flags at
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CY_PSOC6_PIN_FLAGS().
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compatible: "cypress,psoc6-pinctrl"
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include: [base.yaml, pincfg-node.yaml]
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 1
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child-binding:
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description: cypress pins
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properties:
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"cypress,pins":
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type: phandle-array
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