drivers: flash: Add support for STM32L0X
Add support for STM32L0X using the generic STM32 backend. This is quite a significant change since the L0 series uses a slightly different flash controller. Refactor the generic backend to better support different block sizes and the L0's register interface. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
This commit is contained in:
Andreas Sandberg
Anas Nashif
parent
b9da052e51
commit
69f0e3b15f
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@ -7,12 +7,13 @@
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config SOC_FLASH_STM32
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bool "STM32 flash driver"
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depends on SOC_FAMILY_STM32
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X)
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X ||SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X)
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select FLASH_HAS_DRIVER_ENABLED
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default y
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select SOC_FLASH_STM32_V1 if SOC_SERIES_STM32F0X
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select SOC_FLASH_STM32_V1 if SOC_SERIES_STM32F1X
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select SOC_FLASH_STM32_V1 if SOC_SERIES_STM32F3X
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select SOC_FLASH_STM32_V1 if SOC_SERIES_STM32L0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F4X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F7X
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@ -36,6 +36,9 @@ LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
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/* STM32F7: maximum erase time of 4s for a 256K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32F7X)
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#define STM32_FLASH_MAX_ERASE_TIME 4000
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/* STM32L0: maximum erase time of 3.2ms for a 128B page */
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#elif defined(CONFIG_SOC_SERIES_STM32L0X)
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#define STM32_FLASH_MAX_ERASE_TIME 4
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/* STM32L4: maximum erase time of 24.47ms for a 2K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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#define STM32_FLASH_MAX_ERASE_TIME 25
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@ -58,15 +61,14 @@ LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
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#define CFG_HW_FLASH_SEMID 2
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static const struct flash_parameters flash_stm32_parameters = {
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#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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.write_block_size = DT_PROP(DT_INST(0, soc_nv_flash), write_block_size),
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.write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
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/* Some SoCs (L0/L1) use an EEPROM under the hood. Distinguish
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* between them based on the presence of the PECR register. */
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#if defined(FLASH_PECR_ERASE)
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.erase_value = 0,
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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/* as flash node property 'write-block-size' */
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#endif
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/* WARNING: This value may be not valid for L0/L1 chips */
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.erase_value = 0xff,
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#endif
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};
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#if defined(CONFIG_MULTITHREADING)
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@ -278,13 +280,39 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
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flash_stm32_sem_give(dev);
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return rc;
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}
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}
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#if defined(FLASH_CR_LOCK)
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if (enable) {
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regs->CR |= FLASH_CR_LOCK;
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LOG_DBG("Enable write protection");
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} else {
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if (regs->CR & FLASH_CR_LOCK) {
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regs->KEYR = FLASH_KEY1;
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regs->KEYR = FLASH_KEY2;
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}
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}
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#else
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if (enable) {
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regs->PECR |= FLASH_PECR_PRGLOCK;
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regs->PECR |= FLASH_PECR_PELOCK;
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} else {
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if (regs->PECR & FLASH_PECR_PRGLOCK) {
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LOG_DBG("Disabling write protection");
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regs->PEKEYR = FLASH_PEKEY1;
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regs->PEKEYR = FLASH_PEKEY2;
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regs->PRGKEYR = FLASH_PRGKEY1;
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regs->PRGKEYR = FLASH_PRGKEY2;
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}
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if (FLASH->PECR & FLASH_PECR_PRGLOCK) {
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LOG_ERR("Unlock failed");
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rc = -EIO;
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}
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}
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#endif
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if (enable) {
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LOG_DBG("Enable write protection");
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} else {
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LOG_DBG("Disable write protection");
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}
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@ -32,6 +32,15 @@ struct flash_stm32_priv {
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struct k_sem sem;
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};
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#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#define FLASH_STM32_WRITE_BLOCK_SIZE \
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DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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/* as flash node property 'write-block-size' */
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#endif
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#define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->driver_data))
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#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
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@ -1,6 +1,7 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Copyright (c) 2019 Linaro Limited
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* Copyright (c) 2020 Andreas Sandberg
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -17,30 +18,113 @@ LOG_MODULE_REGISTER(flash_stm32generic, CONFIG_FLASH_LOG_LEVEL);
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#include "flash_stm32.h"
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/* offset and len must be aligned on 2 for write
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(struct device *dev, off_t offset, uint32_t len,
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bool write)
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{
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return (!write || (offset % 2 == 0 && len % 2 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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#if FLASH_STM32_WRITE_BLOCK_SIZE == 8
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typedef uint64_t flash_prg_t;
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#elif FLASH_STM32_WRITE_BLOCK_SIZE == 4
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typedef uint32_t flash_prg_t;
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#elif FLASH_STM32_WRITE_BLOCK_SIZE == 2
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typedef uint16_t flash_prg_t;
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#else
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#error Unknown write block size
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#endif
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#if defined(FLASH_CR_PER)
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#define FLASH_ERASED_VALUE ((flash_prg_t)-1)
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#elif defined(FLASH_PECR_ERASE)
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#define FLASH_ERASED_VALUE 0
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#else
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#error Unknown erase value
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#endif
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static unsigned int get_page(off_t offset)
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{
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return offset / FLASH_PAGE_SIZE;
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}
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static int write_hword(struct device *dev, off_t offset, uint16_t val)
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#if defined(FLASH_CR_PER)
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static int is_flash_locked(FLASH_TypeDef *regs)
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{
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volatile uint16_t *flash = (uint16_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
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return !!(regs->CR & FLASH_CR_LOCK);
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}
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static void write_enable(FLASH_TypeDef *regs)
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{
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regs->CR |= FLASH_CR_PG;
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}
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static void write_disable(FLASH_TypeDef *regs)
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{
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regs->CR &= (~FLASH_CR_PG);
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}
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static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page)
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{
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/* Set the PER bit and select the page you wish to erase */
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regs->CR |= FLASH_CR_PER;
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regs->AR = CONFIG_FLASH_BASE_ADDRESS + page * FLASH_PAGE_SIZE;
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__DSB();
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/* Set the STRT bit */
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regs->CR |= FLASH_CR_STRT;
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}
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static void erase_page_end(FLASH_TypeDef *regs)
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{
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regs->CR &= ~FLASH_CR_PER;
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}
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#else
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static int is_flash_locked(FLASH_TypeDef *regs)
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{
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return !!(regs->PECR & FLASH_PECR_PRGLOCK);
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}
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static void write_enable(FLASH_TypeDef *regs)
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{
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regs->PECR |= FLASH_PECR_PROG;
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}
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static void write_disable(FLASH_TypeDef *regs)
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{
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/* Clear the PG bit */
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regs->PECR &= ~FLASH_PECR_PROG;
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}
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static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page)
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{
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volatile flash_prg_t *page_base = (flash_prg_t *)(
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CONFIG_FLASH_BASE_ADDRESS + page * FLASH_PAGE_SIZE);
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/* Enable programming in erase mode. An erase is triggered by
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* writing 0 to the first word of a page.
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*/
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regs->PECR |= FLASH_PECR_ERASE;
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regs->PECR |= FLASH_PECR_PROG;
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__DSB();
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*page_base = 0;
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}
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static void erase_page_end(FLASH_TypeDef *regs)
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{
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/* Disable programming */
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regs->PECR &= ~FLASH_PECR_PROG;
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regs->PECR &= ~FLASH_PECR_ERASE;
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}
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#endif
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static int write_value(struct device *dev, off_t offset, flash_prg_t val)
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{
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volatile flash_prg_t *flash = (flash_prg_t *)(
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offset + CONFIG_FLASH_BASE_ADDRESS);
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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if (is_flash_locked(regs)) {
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LOG_ERR("Flash is locked");
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return -EIO;
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}
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@ -51,15 +135,16 @@ static int write_hword(struct device *dev, off_t offset, uint16_t val)
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}
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/* Check if this half word is erased */
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if (*flash != 0xFFFF) {
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if (*flash != FLASH_ERASED_VALUE) {
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LOG_DBG("Flash location not erased");
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return -EIO;
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}
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/* Set the PG bit */
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regs->CR |= FLASH_CR_PG;
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/* Enable writing */
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write_enable(regs);
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/* Flush the register write */
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tmp = regs->CR;
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/* Make sure the register write has taken effect */
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__DSB();
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/* Perform the data write operation at the desired memory address */
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*flash = val;
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@ -67,21 +152,31 @@ static int write_hword(struct device *dev, off_t offset, uint16_t val)
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(dev);
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/* Clear the PG bit */
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regs->CR &= (~FLASH_CR_PG);
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/* Disable writing */
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write_disable(regs);
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return rc;
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}
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static int erase_page(struct device *dev, unsigned int page)
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/* offset and len must be aligned on 2 for write
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(struct device *dev, off_t offset, uint32_t len,
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bool write)
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{
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return (!write || (offset % 2 == 0 && len % 2 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
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unsigned int len)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t page_address = CONFIG_FLASH_BASE_ADDRESS;
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uint32_t tmp;
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int rc;
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int i, rc = 0;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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if (is_flash_locked(regs)) {
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LOG_ERR("Flash is locked");
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return -EIO;
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}
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@ -91,35 +186,12 @@ static int erase_page(struct device *dev, unsigned int page)
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return rc;
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}
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/* Calculate the flash page address */
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page_address += page * FLASH_PAGE_SIZE;
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for (i = get_page(offset); i <= get_page(offset + len - 1); ++i) {
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erase_page_begin(regs, i);
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__DSB();
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rc = flash_stm32_wait_flash_idle(dev);
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erase_page_end(regs);
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/* Set the PER bit and select the page you wish to erase */
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regs->CR |= FLASH_CR_PER;
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regs->AR = page_address;
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/* Set the STRT bit */
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regs->CR |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->CR;
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
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unsigned int len)
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{
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int i, rc = 0;
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(dev, i);
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if (rc < 0) {
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break;
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}
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@ -132,9 +204,11 @@ int flash_stm32_write_range(struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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const flash_prg_t *values = (const flash_prg_t *)data;
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for (i = 0; i < len; i += 2, offset += 2U) {
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rc = write_hword(dev, offset, ((const uint16_t *) data)[i>>1]);
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for (i = 0; i < len / sizeof(flash_prg_t); i++) {
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rc = write_value(dev, offset + i * sizeof(flash_prg_t),
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values[i]);
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if (rc < 0) {
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return rc;
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}
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@ -42,7 +42,6 @@
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label = "RTC_0";
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};
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/* Driver does not currently support the l0 flash controller */
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32l0-flash-controller";
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label = "FLASH_CTRL";
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