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treewide: Update clock control API usage

Browse source 
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t)

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt 2023-03-28 08:24:07 +02:00 committed by Carles Cufí
parent 688e255e6e
commit 6b532ff43e
88 changed files with 160 additions and 160 deletions
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2
drivers/adc/adc_gd32.c
View file

@ -383,7 +383,7 @@ static int adc_gd32_init(const struct device *dev)
#endif
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);

4
drivers/adc/adc_npcx.c
View file

@ -784,14 +784,14 @@ static int adc_npcx_init(const struct device *dev)
data->adc_dev = dev;
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on ADC clock fail %d", ret);
return ret;
}
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &data->input_clk);
if (ret < 0) {
LOG_ERR("Get ADC clock rate error %d", ret);

2
drivers/adc/adc_sam_afec.c
View file

@ -298,7 +298,7 @@ static int adc_sam_init(const struct device *dev)
/* Enable AFEC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
/* Connect pins to the peripheral */
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);

4
drivers/adc/adc_stm32.c
View file

@ -1366,7 +1366,7 @@ static int adc_stm32_init(const struct device *dev)
#endif
if (clock_control_on(clk,
(clock_control_subsys_t *) &config->pclken) != 0) {
(clock_control_subsys_t) &config->pclken) != 0) {
return -EIO;
}
@ -1504,7 +1504,7 @@ static int adc_stm32_init(const struct device *dev)
uint32_t adc_rate, wait_cycles;
if (clock_control_get_rate(clk,
(clock_control_subsys_t *) &config->pclken, &adc_rate) < 0) {
(clock_control_subsys_t) &config->pclken, &adc_rate) < 0) {
LOG_ERR("ADC clock rate get error.");
}

6
drivers/can/can_rcar.c
View file

@ -1015,19 +1015,19 @@ static int can_rcar_init(const struct device *dev)
/* reset the registers */
ret = clock_control_off(config->clock_dev,
(clock_control_subsys_t *)&config->mod_clk);
(clock_control_subsys_t)&config->mod_clk);
if (ret < 0) {
return ret;
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t *)&config->mod_clk);
(clock_control_subsys_t)&config->mod_clk);
if (ret < 0) {
return ret;
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t *)&config->bus_clk);
(clock_control_subsys_t)&config->bus_clk);
if (ret < 0) {
return ret;
}

2
drivers/can/can_sam.c
View file

@ -47,7 +47,7 @@ static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
/* Enable CAN clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&sam_cfg->clock_cfg);
(clock_control_subsys_t)&sam_cfg->clock_cfg);
}
static int can_sam_init(const struct device *dev)

4
drivers/can/can_stm32.c
View file

@ -532,7 +532,7 @@ static int can_stm32_get_core_clock(const struct device *dev, uint32_t *rate)
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
ret = clock_control_get_rate(clock,
(clock_control_subsys_t *) &cfg->pclken,
(clock_control_subsys_t) &cfg->pclken,
rate);
if (ret != 0) {
LOG_ERR("Failed call clock_control_get_rate: return [%d]", ret);
@ -589,7 +589,7 @@ static int can_stm32_init(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clock, (clock_control_subsys_t *) &cfg->pclken);
ret = clock_control_on(clock, (clock_control_subsys_t) &cfg->pclken);
if (ret != 0) {
LOG_ERR("HAL_CAN_Init clock control on failed: %d", ret);
return -EIO;

2
drivers/can/can_stm32h7.c
View file

@ -58,7 +58,7 @@ static int can_stm32h7_clock_enable(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clk, (clock_control_subsys_t *)&stm32h7_cfg->pclken);
ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken);
if (ret != 0) {
LOG_ERR("failure enabling clock");
return ret;

4
drivers/counter/counter_gd32_timer.c
View file

@ -431,9 +431,9 @@ static int counter_gd32_timer_init(const struct device *dev)
uint32_t pclk;
clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid, &pclk);
(clock_control_subsys_t)&cfg->clkid, &pclk);
data->freq = pclk / (cfg->prescaler + 1);

4
drivers/counter/counter_ll_stm32_rtc.c
View file

@ -398,7 +398,7 @@ static int rtc_stm32_init(const struct device *dev)
}
/* Enable RTC bus clock */
if (clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken[0]) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}
@ -411,7 +411,7 @@ static int rtc_stm32_init(const struct device *dev)
/* Enable RTC clock source */
if (clock_control_configure(clk,
(clock_control_subsys_t *) &cfg->pclken[1],
(clock_control_subsys_t) &cfg->pclken[1],
NULL) != 0) {
LOG_ERR("clock configure failed\n");
return -EIO;

4
drivers/counter/counter_ll_stm32_timer.c
View file

@ -372,7 +372,7 @@ static int counter_stm32_get_tim_clk(const struct stm32_pclken *pclken, uint32_t
return -ENODEV;
}
r = clock_control_get_rate(clk, (clock_control_subsys_t *)pclken,
r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
&bus_clk);
if (r < 0) {
return r;
@ -458,7 +458,7 @@ static int counter_stm32_init_timer(const struct device *dev)
/* initialize clock and check its speed */
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t *)&cfg->pclken);
(clock_control_subsys_t)&cfg->pclken);
if (r < 0) {
LOG_ERR("Could not initialize clock (%d)", r);
return r;

2
drivers/counter/counter_sam_tc.c
View file

@ -325,7 +325,7 @@ static int counter_sam_initialize(const struct device *dev)
/* Enable channel's clock */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg[dev_cfg->tc_chan_num]);
(clock_control_subsys_t)&dev_cfg->clock_cfg[dev_cfg->tc_chan_num]);
/* Clock and Mode Selection */
tc_ch->TC_CMR = dev_cfg->reg_cmr;

6
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -155,9 +155,9 @@ static int dtmr_cmsdk_apb_init(const struct device *dev)
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_dss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_as);
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */

6
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -155,9 +155,9 @@ static int tmr_cmsdk_apb_init(const struct device *dev)
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_as);
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */

2
drivers/crypto/crypto_stm32.c
View file

@ -458,7 +458,7 @@ static int crypto_stm32_init(const struct device *dev)
return -ENODEV;
}
if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}

2
drivers/dac/dac_esp32.c
View file

@ -66,7 +66,7 @@ static int dac_esp32_init(const struct device *dev)
}
if (clock_control_on(cfg->clock_dev,
(clock_control_subsys_t *) &cfg->clock_subsys) != 0) {
(clock_control_subsys_t) &cfg->clock_subsys) != 0) {
LOG_ERR("DAC clock setup failed (%d)", -EIO);
return -EIO;
}

2
drivers/dac/dac_gd32.c
View file

@ -156,7 +156,7 @@ static int dac_gd32_init(const struct device *dev)
}
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);

2
drivers/dac/dac_sam.c
View file

@ -135,7 +135,7 @@ static int dac_sam_init(const struct device *dev)
/* Enable DAC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
(clock_control_subsys_t)&dev_cfg->clock_cfg);
retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {

2
drivers/dac/dac_stm32.c
View file

@ -127,7 +127,7 @@ static int dac_stm32_init(const struct device *dev)
}
if (clock_control_on(clk,
(clock_control_subsys_t *) &cfg->pclken) != 0) {
(clock_control_subsys_t) &cfg->pclken) != 0) {
return -EIO;
}

8
drivers/disk/sdmmc_stm32.c
View file

@ -139,7 +139,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
if (DT_INST_NUM_CLOCKS(0) > 1) {
if (clock_control_configure(clock,
(clock_control_subsys_t *)&priv->pclken[1],
(clock_control_subsys_t)&priv->pclken[1],
NULL) != 0) {
LOG_ERR("Failed to enable SDMMC domain clock");
return -EIO;
@ -150,7 +150,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
uint32_t sdmmc_clock_rate;
if (clock_control_get_rate(clock,
(clock_control_subsys_t *)&priv->pclken[1],
(clock_control_subsys_t)&priv->pclken[1],
&sdmmc_clock_rate) != 0) {
LOG_ERR("Failed to get SDMMC domain clock rate");
return -EIO;
@ -163,7 +163,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
}
/* Enable the APB clock for stm32_sdmmc */
return clock_control_on(clock, (clock_control_subsys_t *)&priv->pclken[0]);
return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]);
}
static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
@ -173,7 +173,7 @@ static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
return clock_control_off(clock,
(clock_control_subsys_t *)&priv->pclken);
(clock_control_subsys_t)&priv->pclken);
}
#if STM32_SDMMC_USE_DMA

2
drivers/dma/dma_gd32.c
View file

@ -602,7 +602,7 @@ static int dma_gd32_init(const struct device *dev)
const struct dma_gd32_config *cfg = dev->config;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
(void)reset_line_toggle_dt(&cfg->reset);

2
drivers/dma/dma_sam_xdmac.c
View file

@ -360,7 +360,7 @@ static int sam_xdmac_initialize(const struct device *dev)
/* Enable XDMAC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Disable all channels */
xdmac->XDMAC_GD = UINT32_MAX;

2
drivers/dma/dma_stm32.c
View file

@ -635,7 +635,7 @@ static int dma_stm32_init(const struct device *dev)
}
if (clock_control_on(clk,
(clock_control_subsys_t *) &config->pclken) != 0) {
(clock_control_subsys_t) &config->pclken) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}

2
drivers/dma/dma_stm32_bdma.c
View file

@ -786,7 +786,7 @@ static int bdma_stm32_init(const struct device *dev)
}
if (clock_control_on(clk,
(clock_control_subsys_t *) &config->pclken) != 0) {
(clock_control_subsys_t) &config->pclken) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}

2
drivers/dma/dma_stm32u5.c
View file

@ -647,7 +647,7 @@ static int dma_stm32_init(const struct device *dev)
const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (clock_control_on(clk,
(clock_control_subsys_t *) &config->pclken) != 0) {
(clock_control_subsys_t) &config->pclken) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}

2
drivers/dma/dmamux_stm32.c
View file

@ -287,7 +287,7 @@ static int dmamux_stm32_init(const struct device *dev)
}
if (clock_control_on(clk,
(clock_control_subsys_t *) &config->pclken) != 0) {
(clock_control_subsys_t) &config->pclken) != 0) {
LOG_ERR("clock op failed\n");
return -EIO;
}

2
drivers/entropy/entropy_sam.c
View file

@ -170,7 +170,7 @@ static int entropy_sam_init(const struct device *dev)
/* Enable TRNG in PMC */
const struct atmel_sam_pmc_config clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0);
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&clock_cfg);
(clock_control_subsys_t)&clock_cfg);
/* Enable the TRNG */
trng->TRNG_CR = TRNG_CR_KEY_PASSWD | TRNG_CR_ENABLE;

4
drivers/entropy/entropy_stm32.c
View file

@ -590,13 +590,13 @@ static int entropy_stm32_rng_init(const struct device *dev)
}
res = clock_control_on(dev_data->clock,
(clock_control_subsys_t *)&dev_cfg->pclken[0]);
(clock_control_subsys_t)&dev_cfg->pclken[0]);
__ASSERT_NO_MSG(res == 0);
/* Configure domain clock if any */
if (DT_INST_NUM_CLOCKS(0) > 1) {
res = clock_control_configure(dev_data->clock,
(clock_control_subsys_t *)&dev_cfg->pclken[1],
(clock_control_subsys_t)&dev_cfg->pclken[1],
NULL);
__ASSERT(res == 0, "Could not select RNG domain clock");
}

2
drivers/espi/espi_npcx.c
View file

@ -1207,7 +1207,7 @@ static int espi_npcx_init(const struct device *dev)
}
/* Turn on eSPI device clock first */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on eSPI clock fail %d", ret);

2
drivers/espi/host_subs_npcx.c
View file

@ -1090,7 +1090,7 @@ int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
return -ENODEV;
}
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&host_sub_cfg.clks_list[i]);
if (ret < 0) {
return ret;

6
drivers/ethernet/eth_dwmac_stm32h7x.c
View file

@ -57,9 +57,9 @@ int dwmac_bus_init(struct dwmac_priv *p)
return -ENODEV;
}
ret = clock_control_on(p->clock, (clock_control_subsys_t *)&pclken);
ret |= clock_control_on(p->clock, (clock_control_subsys_t *)&pclken_tx);
ret |= clock_control_on(p->clock, (clock_control_subsys_t *)&pclken_rx);
ret = clock_control_on(p->clock, (clock_control_subsys_t)&pclken);
ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_tx);
ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_rx);
if (ret) {
LOG_ERR("Failed to enable ethernet clock");
return -EIO;

2
drivers/ethernet/eth_sam_gmac.c
View file

@ -1779,7 +1779,7 @@ static int eth_initialize(const struct device *dev)
#ifdef CONFIG_SOC_FAMILY_SAM
/* Enable GMAC module's clock */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
#else
/* Enable MCLK clock on GMAC */
MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;

12
drivers/ethernet/eth_stm32_hal.c
View file

@ -1142,14 +1142,14 @@ static int eth_initialize(const struct device *dev)
/* enable clock */
ret = clock_control_on(dev_data->clock,
(clock_control_subsys_t *)&cfg->pclken);
(clock_control_subsys_t)&cfg->pclken);
ret |= clock_control_on(dev_data->clock,
(clock_control_subsys_t *)&cfg->pclken_tx);
(clock_control_subsys_t)&cfg->pclken_tx);
ret |= clock_control_on(dev_data->clock,
(clock_control_subsys_t *)&cfg->pclken_rx);
(clock_control_subsys_t)&cfg->pclken_rx);
#if DT_INST_CLOCKS_HAS_NAME(0, mac_clk_ptp)
ret |= clock_control_on(dev_data->clock,
(clock_control_subsys_t *)&cfg->pclken_ptp);
(clock_control_subsys_t)&cfg->pclken_ptp);
#endif
if (ret) {
@ -1889,9 +1889,9 @@ static int ptp_stm32_init(const struct device *port)
/* Query ethernet clock rate */
ret = clock_control_get_rate(eth_dev_data->clock,
#if defined(CONFIG_SOC_SERIES_STM32H7X)
(clock_control_subsys_t *)&eth_cfg->pclken,
(clock_control_subsys_t)&eth_cfg->pclken,
#else
(clock_control_subsys_t *)&eth_cfg->pclken_ptp,
(clock_control_subsys_t)&eth_cfg->pclken_ptp,
#endif /* CONFIG_SOC_SERIES_STM32H7X */
&ptp_hclk_rate);
if (ret) {

2
drivers/flash/flash_stm32.c
View file

@ -536,7 +536,7 @@ static int stm32_flash_init(const struct device *dev)
}
/* enable clock */
if (clock_control_on(clk, (clock_control_subsys_t *)&p->pclken) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
LOG_ERR("Failed to enable clock");
return -EIO;
}

2
drivers/flash/flash_stm32h7x.c
View file

@ -672,7 +672,7 @@ static int stm32h7_flash_init(const struct device *dev)
}
/* enable clock */
if (clock_control_on(clk, (clock_control_subsys_t *)&p->pclken) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
LOG_ERR("Failed to enable clock");
return -EIO;
}

6
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -246,9 +246,9 @@ static int gpio_cmsdk_ahb_init(const struct device *dev)
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->gpio_cc_as);
clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_ss);
clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_dss);
clock_control_on(clk, (clock_control_subsys_t) &cfg->gpio_cc_as);
clock_control_off(clk, (clock_control_subsys_t) &cfg->gpio_cc_ss);
clock_control_off(clk, (clock_control_subsys_t) &cfg->gpio_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */

4
drivers/gpio/gpio_gd32.c
View file

@ -349,9 +349,9 @@ static int gpio_gd32_init(const struct device *port)
const struct gpio_gd32_config *config = port->config;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid);
(clock_control_subsys_t)&config->clkid);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid_exti);
(clock_control_subsys_t)&config->clkid_exti);
(void)reset_line_toggle_dt(&config->reset);

2
drivers/gpio/gpio_rcar.c
View file

@ -253,7 +253,7 @@ static int gpio_rcar_init(const struct device *dev)
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t *) &config->mod_clk);
(clock_control_subsys_t) &config->mod_clk);
if (ret < 0) {
return ret;

2
drivers/gpio/gpio_sam.c
View file

@ -310,7 +310,7 @@ int gpio_sam_init(const struct device *dev)
/* Enable GPIO clock in PMC. This is necessary to enable interrupts */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
cfg->config_func(dev);

2
drivers/gpio/gpio_sam4l.c
View file

@ -234,7 +234,7 @@ int gpio_sam_init(const struct device *dev)
/* Enable GPIO clock in PM */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
cfg->config_func(dev);

6
drivers/gpio/gpio_stm32.c
View file

@ -279,10 +279,10 @@ static int gpio_stm32_clock_request(const struct device *dev, bool on)
if (on) {
ret = clock_control_on(clk,
(clock_control_subsys_t *)&cfg->pclken);
(clock_control_subsys_t)&cfg->pclken);
} else {
ret = clock_control_off(clk,
(clock_control_subsys_t *)&cfg->pclken);
(clock_control_subsys_t)&cfg->pclken);
}
if (ret != 0) {
@ -385,7 +385,7 @@ static int gpio_stm32_enable_int(int port, int pin)
int ret;
/* Enable SYSCFG clock */
ret = clock_control_on(clk, (clock_control_subsys_t *) &pclken);
ret = clock_control_on(clk, (clock_control_subsys_t) &pclken);
if (ret != 0) {
return ret;
}

2
drivers/hwinfo/hwinfo_sam_rstc.c
View file

@ -63,7 +63,7 @@ static int hwinfo_rstc_init(const struct device *dev)
/* Enable RSTC in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&clock_cfg);
(clock_control_subsys_t)&clock_cfg);
/* Get current Mode Register value */
mode = regs->RSTC_MR;

4
drivers/i2c/i2c_gd32.c
View file

@ -504,7 +504,7 @@ static int i2c_gd32_configure(const struct device *dev,
I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid,
(clock_control_subsys_t)&cfg->clkid,
&pclk1);
/* i2c clock frequency, us */
@ -668,7 +668,7 @@ static int i2c_gd32_init(const struct device *dev)
k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);

6
drivers/i2c/i2c_ll_stm32.c
View file

@ -61,7 +61,7 @@ int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
}
} else {
if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t *) &cfg->pclken[0],
(clock_control_subsys_t) &cfg->pclken[0],
&clock) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
return -EIO;
@ -380,7 +380,7 @@ static int i2c_stm32_activate(const struct device *dev)
/* Enable device clock. */
if (clock_control_on(clk,
(clock_control_subsys_t *) &cfg->pclken[0]) != 0) {
(clock_control_subsys_t) &cfg->pclken[0]) != 0) {
LOG_ERR("i2c: failure enabling clock");
return -EIO;
}
@ -418,7 +418,7 @@ static int i2c_stm32_init(const struct device *dev)
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
/* Enable I2C clock source */
ret = clock_control_configure(clk,
(clock_control_subsys_t *) &cfg->pclken[1],
(clock_control_subsys_t) &cfg->pclken[1],
NULL);
if (ret < 0) {
return -EIO;

4
drivers/i2c/i2c_npcx_controller.c
View file

@ -1039,7 +1039,7 @@ static int i2c_ctrl_init(const struct device *dev)
/* Turn on device clock first and get source clock freq. */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg) != 0) {
(clock_control_subsys_t) &config->clk_cfg) != 0) {
LOG_ERR("Turn on %s clock fail.", dev->name);
return -EIO;
}
@ -1049,7 +1049,7 @@ static int i2c_ctrl_init(const struct device *dev)
* configuration of the device to meet SMBus timing spec. Please refer
* Table 21/22/23 and section 7.5.9 SMBus Timing for more detail.
*/
if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
if (clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &i2c_rate) != 0) {
LOG_ERR("Get %s clock rate error.", dev->name);
return -EIO;

2
drivers/i2c/i2c_rcar.c
View file

@ -327,7 +327,7 @@ static int i2c_rcar_init(const struct device *dev)
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t *)&config->mod_clk);
(clock_control_subsys_t)&config->mod_clk);
if (ret != 0) {
return ret;

2
drivers/i2c/i2c_sam4l_twim.c
View file

@ -561,7 +561,7 @@ static int i2c_sam_twim_initialize(const struct device *dev)
/* Enable TWIM clock in PM */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
/* Enable the module*/
twim->CR = TWIM_CR_MEN;

2
drivers/i2c/i2c_sam_twi.c
View file

@ -329,7 +329,7 @@ static int i2c_sam_twi_initialize(const struct device *dev)
/* Enable TWI clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Reset TWI module */
twi->TWI_CR = TWI_CR_SWRST;

2
drivers/i2c/i2c_sam_twihs.c
View file

@ -300,7 +300,7 @@ static int i2c_sam_twihs_initialize(const struct device *dev)
/* Enable TWIHS clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Reset the module */
twihs->TWIHS_CR = TWIHS_CR_SWRST;

4
drivers/i2s/i2s_ll_stm32.c
View file

@ -108,7 +108,7 @@ static int i2s_stm32_enable_clock(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken[0]);
ret = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]);
if (ret != 0) {
LOG_ERR("Could not enable I2S clock");
return -EIO;
@ -117,7 +117,7 @@ static int i2s_stm32_enable_clock(const struct device *dev)
if (cfg->pclk_len > 1) {
/* Enable I2S clock source */
ret = clock_control_configure(clk,
(clock_control_subsys_t *) &cfg->pclken[1],
(clock_control_subsys_t)&cfg->pclken[1],
NULL);
if (ret < 0) {
LOG_ERR("Could not configure I2S domain clock");

2
drivers/i2s/i2s_sam_ssc.c
View file

@ -977,7 +977,7 @@ static int i2s_sam_initialize(const struct device *dev)
/* Enable SSC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
(clock_control_subsys_t)&dev_cfg->clock_cfg);
/* Reset the module, disable receiver & transmitter */
ssc->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST;

2
drivers/interrupt_controller/intc_mchp_ecia_xec.c
View file

@ -522,7 +522,7 @@ static int xec_ecia_init(const struct device *dev)
}
ret = clock_control_on(clk_dev,
(clock_control_subsys_t *)&cfg->clk_ctrl);
(clock_control_subsys_t)&cfg->clk_ctrl);
if (ret < 0) {
return ret;
}

2
drivers/ipm/ipm_stm32_hsem.c
View file

@ -164,7 +164,7 @@ static int stm32_hsem_mailbox_init(const struct device *dev)
}
/* Enable clock */
if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) {
LOG_WRN("Failed to enable clock");
return -EIO;
}

2
drivers/ipm/ipm_stm32_ipcc.c
View file

@ -253,7 +253,7 @@ static int stm32_ipcc_mailbox_init(const struct device *dev)
/* enable clock */
if (clock_control_on(clk,
(clock_control_subsys_t *)&cfg->pclken) != 0) {
(clock_control_subsys_t)&cfg->pclken) != 0) {
return -EIO;
}

2
drivers/kscan/kscan_npcx.c
View file

@ -425,7 +425,7 @@ static int kscan_npcx_init(const struct device *dev)
}
/* Turn on KBSCAN controller device clock */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on KBSCAN clock fail %d", ret);
}

2
drivers/memc/memc_sam_smc.c
View file

@ -38,7 +38,7 @@ static int memc_smc_init(const struct device *dev)
/* Enable SMC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {

2
drivers/memc/memc_stm32.c
View file

@ -49,7 +49,7 @@ static int memc_stm32_init(const struct device *dev)
return -ENODEV;
}
r = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken);
r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken);
if (r < 0) {
LOG_ERR("Could not initialize FMC clock (%d)", r);
return r;

4
drivers/peci/peci_npcx.c
View file

@ -244,13 +244,13 @@ static int peci_npcx_init(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on PECI clock fail %d", ret);
return ret;
}
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&config->clk_cfg,
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg,
&data->peci_src_clk_freq);
if (ret < 0) {
LOG_ERR("Get PECI source clock rate error %d", ret);

2
drivers/pinctrl/pinctrl_gd32_af.c
View file

@ -89,7 +89,7 @@ static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
af = GD32_AF_GET(pin);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&clkid);
(clock_control_subsys_t)&clkid);
if (af != GD32_ANALOG) {
mode = GPIO_MODE_AF;

4
drivers/pinctrl/pinctrl_gd32_afio.c
View file

@ -69,7 +69,7 @@ static int afio_init(const struct device *dev)
ARG_UNUSED(dev);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&clkid);
(clock_control_subsys_t)&clkid);
#ifdef AFIO_CPSCTL
if (DT_PROP(AFIO_NODE, enable_cps)) {
@ -139,7 +139,7 @@ static void configure_pin(pinctrl_soc_pin_t pin)
}
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&clkid);
(clock_control_subsys_t)&clkid);
reg_val = *reg;
reg_val &= ~GPIO_MODE_MASK(pin_num);

2
drivers/ps2/ps2_npcx_controller.c
View file

@ -338,7 +338,7 @@ static int ps2_npcx_ctrl_init(const struct device *dev)
/* Turn on PS/2 controller device clock */
ret = clock_control_on(clk_dev,
(clock_control_subsys_t *)&config->clk_cfg);
(clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on PS/2 clock fail %d", ret);
return ret;

4
drivers/pwm/pwm_gd32.c
View file

@ -155,7 +155,7 @@ static int pwm_gd32_init(const struct device *dev)
int ret;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid);
(clock_control_subsys_t)&config->clkid);
(void)reset_line_toggle_dt(&config->reset);
@ -167,7 +167,7 @@ static int pwm_gd32_init(const struct device *dev)
/* cache timer clock value */
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid,
(clock_control_subsys_t)&config->clkid,
&data->tim_clk);
/* basic timer operation: edge aligned, up counting, shadowed CAR */

4
drivers/pwm/pwm_npcx.c
View file

@ -189,14 +189,14 @@ static int pwm_npcx_init(const struct device *dev)
}
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on PWM clock fail %d", ret);
return ret;
}
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &data->cycles_per_sec);
if (ret < 0) {
LOG_ERR("Get PWM clock rate error %d", ret);

4
drivers/pwm/pwm_rcar.c
View file

@ -228,12 +228,12 @@ static int pwm_rcar_init(const struct device *dev)
return ret;
}
ret = clock_control_on(config->clock_dev, (clock_control_subsys_t *)&config->mod_clk);
ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->mod_clk);
if (ret < 0) {
return ret;
}
ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t *)&config->core_clk,
ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->core_clk,
&data->clk_rate);
if (ret < 0) {

2
drivers/pwm/pwm_sam.c
View file

@ -105,7 +105,7 @@ static int sam_pwm_init(const struct device *dev)
/* Enable PWM clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&config->clock_cfg);
(clock_control_subsys_t)&config->clock_cfg);
retval = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {

4
drivers/pwm/pwm_stm32.c
View file

@ -158,7 +158,7 @@ static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
r = clock_control_get_rate(clk, (clock_control_subsys_t *)pclken,
r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
&bus_clk);
if (r < 0) {
return r;
@ -643,7 +643,7 @@ static int pwm_stm32_init(const struct device *dev)
return -ENODEV;
}
r = clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken);
r = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken);
if (r < 0) {
LOG_ERR("Could not initialize clock (%d)", r);
return r;

4
drivers/sensor/nuvoton_tach_npcx/tach_nuvoton_npcx.c
View file

@ -320,14 +320,14 @@ static int tach_npcx_init(const struct device *dev)
}
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on tachometer clock fail %d", ret);
return ret;
}
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&config->clk_cfg, &data->input_clk);
if (ret < 0) {
LOG_ERR("Get tachometer clock rate error %d", ret);

2
drivers/sensor/qdec_sam/qdec_sam.c
View file

@ -107,7 +107,7 @@ static int qdec_sam_initialize(const struct device *dev)
for (int i = 0; i < ARRAY_SIZE(dev_cfg->clock_cfg); i++) {
/* Enable TC clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&dev_cfg->clock_cfg[i]);
(clock_control_subsys_t)&dev_cfg->clock_cfg[i]);
}
qdec_sam_configure(dev);

6
drivers/serial/uart_cmsdk_apb.c
View file

@ -135,9 +135,9 @@ static int uart_cmsdk_apb_init(const struct device *dev)
}
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_dss);
clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_as);
clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_ss);
clock_control_on(clk, (clock_control_subsys_t) &data->uart_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */

4
drivers/serial/uart_npcx.c
View file

@ -469,7 +469,7 @@ static int uart_npcx_init(const struct device *dev)
}
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on UART clock fail %d", ret);
return ret;
@ -479,7 +479,7 @@ static int uart_npcx_init(const struct device *dev)
* If apb2's clock is not 15MHz, we need to find the other optimized
* values of UPSR and UBAUD for baud rate 115200.
*/
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)&config->clk_cfg,
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)&config->clk_cfg,
&uart_rate);
if (ret < 0) {
LOG_ERR("Get UART clock rate error %d", ret);

4
drivers/serial/uart_rcar.c
View file

@ -279,13 +279,13 @@ static int uart_rcar_init(const struct device *dev)
}
ret = clock_control_on(config->clock_dev,
(clock_control_subsys_t *)&config->mod_clk);
(clock_control_subsys_t)&config->mod_clk);
if (ret < 0) {
return ret;
}
ret = clock_control_get_rate(config->clock_dev,
(clock_control_subsys_t *)&config->bus_clk,
(clock_control_subsys_t)&config->bus_clk,
&data->clk_rate);
if (ret < 0) {
return ret;

2
drivers/serial/uart_sam.c
View file

@ -390,7 +390,7 @@ static int uart_sam_init(const struct device *dev)
/* Enable UART clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
/* Connect pins to the peripheral */
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);

2
drivers/serial/usart_gd32.c
View file

@ -86,7 +86,7 @@ static int usart_gd32_init(const struct device *dev)
}
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);

2
drivers/serial/usart_sam.c
View file

@ -484,7 +484,7 @@ static int usart_sam_init(const struct device *dev)
/* Enable USART clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
/* Connect pins to the peripheral */
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);

4
drivers/spi/spi_gd32.c
View file

@ -173,7 +173,7 @@ static int spi_gd32_configure(const struct device *dev,
}
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid,
(clock_control_subsys_t)&cfg->clkid,
&bus_freq);
for (uint8_t i = 0U; i <= GD32_SPI_PSC_MAX; i++) {
@ -583,7 +583,7 @@ int spi_gd32_init(const struct device *dev)
#endif
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(clock_control_subsys_t)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);

2
drivers/spi/spi_npcx_fiu.c
View file

@ -152,7 +152,7 @@ static int spi_npcx_fiu_init(const struct device *dev)
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev,
(clock_control_subsys_t *)&config->clk_cfg);
(clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on FIU clock fail %d", ret);
return ret;

2
drivers/spi/spi_sam.c
View file

@ -839,7 +839,7 @@ static int spi_sam_init(const struct device *dev)
/* Enable SPI clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&cfg->clock_cfg);
(clock_control_subsys_t)&cfg->clock_cfg);
err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (err < 0) {

4
drivers/timer/npcx_itim_timer.c
View file

@ -317,7 +317,7 @@ static int sys_clock_driver_init(const struct device *dev)
/* Turn on all itim module clocks used for counting */
for (int i = 0; i < ARRAY_SIZE(itim_clk_cfg); i++) {
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
&itim_clk_cfg[i]);
if (ret < 0) {
LOG_ERR("Turn on timer %d clock failed.", i);
@ -329,7 +329,7 @@ static int sys_clock_driver_init(const struct device *dev)
* In npcx series, we use ITIM64 as system kernel timer. Its source
* clock frequency must equal to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
*/
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
&itim_clk_cfg[1], &sys_tmr_rate);
if (ret < 0) {
LOG_ERR("Get ITIM64 clock rate failed %d", ret);

2
drivers/timer/rcar_cmt_timer.c
View file

@ -101,7 +101,7 @@ static int sys_clock_driver_init(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clk, (clock_control_subsys_t *)&mod_clk);
ret = clock_control_on(clk, (clock_control_subsys_t)&mod_clk);
if (ret < 0) {
return ret;
}

10
drivers/timer/stm32_lptim_timer.c
View file

@ -181,12 +181,12 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
}
if (ticks == K_TICKS_FOREVER) {
clock_control_off(clk_ctrl, (clock_control_subsys_t *) &lptim_clk[0]);
clock_control_off(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
return;
}
/* if LPTIM clock was previously stopped, it must now be restored */
clock_control_on(clk_ctrl, (clock_control_subsys_t *) &lptim_clk[0]);
clock_control_on(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
/* passing ticks==1 means "announce the next tick",
* ticks value of zero (or even negative) is legal and
@ -326,7 +326,7 @@ static int sys_clock_driver_init(const struct device *dev)
}
/* Enable LPTIM bus clock */
err = clock_control_on(clk_ctrl, (clock_control_subsys_t *) &lptim_clk[0]);
err = clock_control_on(clk_ctrl, (clock_control_subsys_t) &lptim_clk[0]);
if (err < 0) {
return -EIO;
}
@ -339,14 +339,14 @@ static int sys_clock_driver_init(const struct device *dev)
/* Enable LPTIM clock source */
err = clock_control_configure(clk_ctrl,
(clock_control_subsys_t *) &lptim_clk[1],
(clock_control_subsys_t) &lptim_clk[1],
NULL);
if (err < 0) {
return -EIO;
}
/* Get LPTIM clock freq */
err = clock_control_get_rate(clk_ctrl, (clock_control_subsys_t *) &lptim_clk[1],
err = clock_control_get_rate(clk_ctrl, (clock_control_subsys_t) &lptim_clk[1],
&lptim_clock_freq);
if (err < 0) {

4
drivers/usb/device/usb_dc_sam_usbhs.c
View file

@ -315,7 +315,7 @@ int usb_dc_attach(void)
/* Enable USBHS clock in PMC */
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&clock_cfg);
(clock_control_subsys_t)&clock_cfg);
/* Enable the USB controller in device mode with the clock frozen */
USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE |
@ -375,7 +375,7 @@ int usb_dc_detach(void)
/* Disable USBHS clock in PMC */
(void)clock_control_off(SAM_DT_PMC_CONTROLLER,
(clock_control_subsys_t *)&clock_cfg);
(clock_control_subsys_t)&clock_cfg);
/* Disable interrupt */
irq_disable(DT_INST_IRQN(0));

8
drivers/usb/device/usb_dc_stm32.c
View file

@ -219,14 +219,14 @@ static int usb_dc_stm32_clock_enable(void)
#endif /* CONFIG_SOC_SERIES_STM32U5X */
if (DT_INST_NUM_CLOCKS(0) > 1) {
if (clock_control_configure(clk, (clock_control_subsys_t *)&pclken[1],
if (clock_control_configure(clk, (clock_control_subsys_t)&pclken[1],
NULL) != 0) {
LOG_ERR("Could not select USB domain clock");
return -EIO;
}
}
if (clock_control_on(clk, (clock_control_subsys_t *)&pclken[0]) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
LOG_ERR("Unable to enable USB clock");
return -EIO;
}
@ -235,7 +235,7 @@ static int usb_dc_stm32_clock_enable(void)
uint32_t usb_clock_rate;
if (clock_control_get_rate(clk,
(clock_control_subsys_t *)&pclken[1],
(clock_control_subsys_t)&pclken[1],
&usb_clock_rate) != 0) {
LOG_ERR("Failed to get USB domain clock rate");
return -EIO;
@ -284,7 +284,7 @@ static int usb_dc_stm32_clock_disable(void)
{
const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (clock_control_off(clk, (clock_control_subsys_t *)&pclken[0]) != 0) {
if (clock_control_off(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
LOG_ERR("Unable to disable USB clock");
return -EIO;
}

4
drivers/watchdog/wdt_wwdg_stm32.c
View file

@ -93,7 +93,7 @@ static uint32_t wwdg_stm32_get_pclk(const struct device *dev)
const struct wwdg_stm32_config *cfg = WWDG_STM32_CFG(dev);
uint32_t pclk_rate;
if (clock_control_get_rate(clk, (clock_control_subsys_t *) &cfg->pclken,
if (clock_control_get_rate(clk, (clock_control_subsys_t) &cfg->pclken,
&pclk_rate) < 0) {
LOG_ERR("Failed call clock_control_get_rate");
return -EIO;
@ -289,7 +289,7 @@ static int wwdg_stm32_init(const struct device *dev)
return -ENODEV;
}
return clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
return clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken);
}
static struct wwdg_stm32_data wwdg_stm32_dev_data = {

4
drivers/watchdog/wdt_wwdgt_gd32.c
View file

@ -57,7 +57,7 @@ static inline uint32_t gd32_wwdgt_calc_ticks(const struct device *dev,
uint32_t pclk;
(void)clock_control_get_rate(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid,
(clock_control_subsys_t)&config->clkid,
&pclk);
return ((timeout * pclk)
@ -204,7 +204,7 @@ static int gd32_wwdgt_init(const struct device *dev)
const struct gd32_wwdgt_config *config = dev->config;
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&config->clkid);
(clock_control_subsys_t)&config->clkid);
(void)reset_line_toggle_dt(&config->reset);
gd32_wwdgt_irq_config(dev);

2
samples/drivers/clock_control_litex/README.rst
View file

@ -57,7 +57,7 @@ The driver is interfaced with the :ref:`Clock Control API <clock_control_api>` f
.phase = 90
};
dev = DEVICE_DT_GET(MMCM);
clock_control_subsys_t sub_system = (clock_control_subsys_t*)&setup;
clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup;
if ((ret = clock_control_on(dev, sub_system)) != 0) {
LOG_ERR("Set CLKOUT%d param error!", setup.clkout_nr);
return ret;

30
samples/drivers/clock_control_litex/src/main.c
View file

@ -66,7 +66,7 @@ int litex_clk_test_getters(const struct device *dev)
uint32_t rate;
int i;
clock_control_subsys_t sub_system = (clock_control_subsys_t *)&setup;
clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup;
printf("Getters test\n");
for (i = 0; i < NCLKOUT; i++) {
@ -96,8 +96,8 @@ int litex_clk_test_single(const struct device *dev)
.phase = LITEX_TEST_SINGLE_PHASE_VAL2,
};
uint32_t ret = 0;
clock_control_subsys_t sub_system1 = (clock_control_subsys_t *)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t *)&setup2;
clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
printf("Single test\n");
ret = clock_control_on(dev, sub_system1);
@ -121,7 +121,7 @@ int litex_clk_test_freq(const struct device *dev)
.duty = LITEX_TEST_FREQUENCY_DUTY_VAL,
.phase = LITEX_TEST_FREQUENCY_PHASE_VAL
};
clock_control_subsys_t sub_system = (clock_control_subsys_t *)&setup;
clock_control_subsys_t sub_system = (clock_control_subsys_t)&setup;
uint32_t i, ret = 0;
printf("Frequency test\n");
@ -131,7 +131,7 @@ int litex_clk_test_freq(const struct device *dev)
i += LITEX_TEST_FREQUENCY_STEP) {
setup.clkout_nr = LITEX_CLK_TEST_CLK1;
setup.rate = i;
sub_system = (clock_control_subsys_t *)&setup;
sub_system = (clock_control_subsys_t)&setup;
/*
* Don't check for ENOTSUP here because it is expected.
* The reason is that set of possible frequencies for
@ -159,7 +159,7 @@ int litex_clk_test_freq(const struct device *dev)
i -= LITEX_TEST_FREQUENCY_STEP) {
setup.clkout_nr = LITEX_CLK_TEST_CLK1;
setup.rate = i;
sub_system = (clock_control_subsys_t *)&setup;
sub_system = (clock_control_subsys_t)&setup;
ret = clock_control_on(dev, sub_system);
if (ret != 0 && ret != -ENOTSUP) {
return ret;
@ -189,8 +189,8 @@ int litex_clk_test_phase(const struct device *dev)
.rate = LITEX_TEST_PHASE_FREQ_VAL,
.duty = LITEX_TEST_PHASE_DUTY_VAL
};
clock_control_subsys_t sub_system1 = (clock_control_subsys_t *)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t *)&setup2;
clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
uint32_t ret = 0;
int i;
@ -205,7 +205,7 @@ int litex_clk_test_phase(const struct device *dev)
for (i = LITEX_TEST_PHASE_MIN; i <= LITEX_TEST_PHASE_MAX;
i += LITEX_TEST_PHASE_STEP) {
setup2.phase = i;
sub_system2 = (clock_control_subsys_t *)&setup2;
sub_system2 = (clock_control_subsys_t)&setup2;
ret = clock_control_on(dev, sub_system2);
if (ret != 0) {
return ret;
@ -232,8 +232,8 @@ int litex_clk_test_duty(const struct device *dev)
.duty = 0
};
uint32_t ret = 0, i;
clock_control_subsys_t sub_system1 = (clock_control_subsys_t *)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t *)&setup2;
clock_control_subsys_t sub_system1 = (clock_control_subsys_t)&setup1;
clock_control_subsys_t sub_system2 = (clock_control_subsys_t)&setup2;
ret = clock_control_on(dev, sub_system1);
if (ret != 0 && ret != -ENOTSUP) {
@ -250,13 +250,13 @@ int litex_clk_test_duty(const struct device *dev)
for (i = LITEX_TEST_DUTY_MIN; i <= LITEX_TEST_DUTY_MAX;
i += LITEX_TEST_DUTY_STEP) {
setup1.duty = i;
sub_system1 = (clock_control_subsys_t *)&setup1;
sub_system1 = (clock_control_subsys_t)&setup1;
ret = clock_control_on(dev, sub_system1);
if (ret != 0) {
return ret;
}
setup2.duty = 100 - i;
sub_system2 = (clock_control_subsys_t *)&setup2;
sub_system2 = (clock_control_subsys_t)&setup2;
ret = clock_control_on(dev, sub_system2);
if (ret != 0) {
return ret;
@ -266,13 +266,13 @@ int litex_clk_test_duty(const struct device *dev)
for (i = LITEX_TEST_DUTY_MAX; i > LITEX_TEST_DUTY_MIN;
i -= LITEX_TEST_DUTY_STEP) {
setup1.duty = i;
sub_system1 = (clock_control_subsys_t *)&setup1;
sub_system1 = (clock_control_subsys_t)&setup1;
ret = clock_control_on(dev, sub_system1);
if (ret != 0) {
return ret;
}
setup2.duty = 100 - i;
sub_system2 = (clock_control_subsys_t *)&setup2;
sub_system2 = (clock_control_subsys_t)&setup2;
ret = clock_control_on(dev, sub_system2);
if (ret != 0) {
return ret;

2
soc/arm/st_stm32/common/stm32_backup_sram.c
View file

@ -32,7 +32,7 @@ static int stm32_backup_sram_init(const struct device *dev)
return -ENODEV;
}
ret = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken);
ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken);
if (ret < 0) {
LOG_ERR("Could not initialize backup SRAM clock (%d)", ret);
return ret;

6
subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_shi_npcx.c
View file

@ -719,7 +719,7 @@ static int shi_npcx_enable(const struct device *dev)
const struct shi_npcx_config *const config = dev->config;
int ret;
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on SHI clock fail %d", ret);
return ret;
@ -761,7 +761,7 @@ static int shi_npcx_disable(const struct device *dev)
return ret;
}
ret = clock_control_off(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_off(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn off SHI clock fail %d", ret);
return ret;
@ -778,7 +778,7 @@ static int shi_npcx_init_registers(const struct device *dev)
const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
/* Turn on shi device clock first */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on SHI clock fail %d", ret);
return ret;