dts: Add Microchip mpfs-icicle device tree

Adding Microchip PolarFire SoC Icicle device tree support

Signed-off-by: Peter McShane <peter.mcshane@microchip.com>

dts/riscv/mpfs-icicle.dtsi

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			clock-frequency = <0>;
+			compatible = "microsemi,miv", "riscv";
+			device_type = "cpu";
+			reg = < 0x01 >;
+			riscv,isa = "rv64imac"; 
+			#status = "disabled";
+		};
+
+		cpu@1 {
+			clock-frequency = <0>;
+			compatible = "microsemi,miv", "riscv";
+			device_type = "cpu";
+			reg = < 0x00 >;
+			riscv,isa = "rv64imafdc";
+			hlic: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		sram0: memory@8000000 {
+			compatible = "mmio-sram";
+			reg = <0x8000000 0x80000>;
+		};
+
+		sram1: memory@80000000 {
+			compatible = "mmio-sram";
+			reg = <0x80000000 0x800000>;
+		};
+
+		plic: interrupt-controller@c000000 {
+			#interrupt-cells = <2>;
+			compatible = "sifive,plic-1.0.0";
+			interrupt-controller;
+			interrupts-extended = <&hlic 11>;
+			reg = <0x0c000000 0x00002000
+			       0x0c002000 0x001fe000
+			       0x0c200000 0x3e000000>;
+			reg-names = "prio", "irq_en", "reg";
+			riscv,max-priority = <7>;
+			riscv,ndev = <187>;
+		};
+			
+		uart0: uart@20000000 {
+			compatible = "ns16550";
+			reg = <0x20000000 0x1000>;
+			clock-frequency = <150000000>;
+			current-speed = <115200>;
+			interrupt-parent = <&plic>;
+			interrupts = <90 1>;
+			label = "UART_0";
+			reg-shift = <2>;
+			status = "disabled";
+		};
+	};
+};