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benchmarking: remove execution benchmarking code

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This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Anas Nashif 2020-09-04 20:39:25 -04:00 committed by Maureen Helm
parent 150c82c8f9
commit 6e27478c3d
29 changed files with 6 additions and 550 deletions
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11
arch/arc/core/isr_wrapper.S
View file

@ -275,10 +275,6 @@ SECTION_FUNC(TEXT, _isr_demux)
push r59 push r59
#endif #endif
#ifdef CONFIG_EXECUTION_BENCHMARKING
bl read_timer_start_of_isr
#endif
#if defined(CONFIG_TRACING_ISR) #if defined(CONFIG_TRACING_ISR)
bl sys_trace_isr_enter bl sys_trace_isr_enter
#endif #endif
@ -299,13 +295,6 @@ irq_hint_handled:
add3 r0, r1, r0 /* table entries are 8-bytes wide */ add3 r0, r1, r0 /* table entries are 8-bytes wide */
ld_s r1, [r0, 4] /* ISR into r1 */ ld_s r1, [r0, 4] /* ISR into r1 */
#ifdef CONFIG_EXECUTION_BENCHMARKING
push_s r0
push_s r1
bl read_timer_end_of_isr
pop_s r1
pop_s r0
#endif
jl_s.d [r1] jl_s.d [r1]
ld_s r0, [r0] /* delay slot: ISR parameter into r0 */ ld_s r0, [r0] /* delay slot: ISR parameter into r0 */

18
arch/arc/core/switch.S
View file

@ -54,17 +54,6 @@ GTEXT(z_arc_switch)
SECTION_FUNC(TEXT, z_arc_switch) SECTION_FUNC(TEXT, z_arc_switch)
#ifdef CONFIG_EXECUTION_BENCHMARKING
push_s r0
push_s r1
push_s blink
bl read_timer_start_of_swap
pop_s blink
pop_s r1
pop_s r0
#endif
/* /*
* r0 = new_thread->switch_handle = switch_to thread, * r0 = new_thread->switch_handle = switch_to thread,
* r1 = &old_thread->switch_handle * r1 = &old_thread->switch_handle
@ -125,13 +114,6 @@ _switch_return_from_coop:
pop_s r3 /* status32 into r3 */ pop_s r3 /* status32 into r3 */
kflag r3 /* write status32 */ kflag r3 /* write status32 */
#ifdef CONFIG_EXECUTION_BENCHMARKING
push_s blink
bl read_timer_end_of_swap
pop_s blink
#endif /* CONFIG_EXECUTION_BENCHMARKING */
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
push_s blink push_s blink

4
arch/arc/core/userspace.S
View file

@ -179,10 +179,6 @@ _arc_go_to_user_space:
mov r30, 0 mov r30, 0
mov blink, 0 mov blink, 0
#ifdef CONFIG_EXECUTION_BENCHMARKING
bl read_timer_end_of_userspace_enter
#endif
rtie rtie
/** /**

9
arch/arm/core/aarch32/isr_wrapper.S
View file

@ -80,10 +80,6 @@ SECTION_FUNC(TEXT, _isr_wrapper)
str r0, [r2, #_kernel_offset_to_nested] str r0, [r2, #_kernel_offset_to_nested]
#endif /* CONFIG_CPU_CORTEX_M */ #endif /* CONFIG_CPU_CORTEX_M */
#ifdef CONFIG_EXECUTION_BENCHMARKING
bl read_timer_start_of_isr
#endif
#ifdef CONFIG_TRACING_ISR #ifdef CONFIG_TRACING_ISR
bl sys_trace_isr_enter bl sys_trace_isr_enter
#endif #endif
@ -187,11 +183,6 @@ _idle_state_cleared:
* in thumb mode */ * in thumb mode */
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */ ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
#ifdef CONFIG_EXECUTION_BENCHMARKING
push {r0, r3} /* Save r0 and r3 into stack */
bl read_timer_end_of_isr
pop {r0, r3} /* Restore r0 and r3 regs */
#endif /* CONFIG_EXECUTION_BENCHMARKING */
blx r3 /* call ISR */ blx r3 /* call ISR */
#if defined(CONFIG_CPU_CORTEX_R) #if defined(CONFIG_CPU_CORTEX_R)

7
arch/arm/core/aarch32/swap.c
View file

@ -7,9 +7,6 @@
#include <kernel.h> #include <kernel.h>
#include <kernel_internal.h> #include <kernel_internal.h>
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_swap(void);
#endif
extern const int _k_neg_eagain; extern const int _k_neg_eagain;
/* The 'key' actually represents the BASEPRI register /* The 'key' actually represents the BASEPRI register
@ -35,10 +32,6 @@ extern const int _k_neg_eagain;
*/ */
int arch_swap(unsigned int key) int arch_swap(unsigned int key)
{ {
#ifdef CONFIG_EXECUTION_BENCHMARKING
read_timer_start_of_swap();
#endif
/* store off key and return value */ /* store off key and return value */
_current->arch.basepri = key; _current->arch.basepri = key;
_current->arch.swap_return_value = _k_neg_eagain; _current->arch.swap_return_value = _k_neg_eagain;

12
arch/arm/core/aarch32/swap_helper.S
View file

@ -337,18 +337,6 @@ _thread_irq_disabled:
pop {r2, lr} pop {r2, lr}
#endif /* CONFIG_BUILTIN_STACK_GUARD */ #endif /* CONFIG_BUILTIN_STACK_GUARD */
#ifdef CONFIG_EXECUTION_BENCHMARKING
push {r0, lr}
bl read_timer_end_of_swap
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r1}
mov lr,r1
#else
pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_EXECUTION_BENCHMARKING */
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
/* Register the context switch */ /* Register the context switch */
push {r0, lr} push {r0, lr}

14
arch/arm/core/aarch32/userspace.S
View file

@ -216,20 +216,6 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
/* restore r0 */ /* restore r0 */
mov r0, lr mov r0, lr
#ifdef CONFIG_EXECUTION_BENCHMARKING
stm sp!,{r0-r3} /* Save regs r0 to r4 on stack */
push {r0, lr}
bl read_timer_end_of_userspace_enter
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r3}
mov lr,r3
#else
pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
ldm sp!,{r0-r3} /* Restore r0 to r3 regs */
#endif /* CONFIG_EXECUTION_BENCHMARKING */
/* change processor mode to unprivileged */ /* change processor mode to unprivileged */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
push {r0, r1, r2, r3} push {r0, r1, r2, r3}

7
arch/common/CMakeLists.txt
View file

@ -1,17 +1,12 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if(CONFIG_GEN_ISR_TABLES OR CONFIG_EXECUTION_BENCHMARKING) if(CONFIG_GEN_ISR_TABLES)
zephyr_library() zephyr_library()
zephyr_library_sources_ifdef( zephyr_library_sources_ifdef(
CONFIG_GEN_ISR_TABLES CONFIG_GEN_ISR_TABLES
sw_isr_common.c sw_isr_common.c
) )
zephyr_library_sources_ifdef(
CONFIG_EXECUTION_BENCHMARKING
timing_info_bench.c
)
endif() endif()
if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND

135
arch/common/timing_info_bench.c
View file

@ -1,135 +0,0 @@
/*
* Copyright (c) 2017 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <kernel_internal.h>
uint64_t arch_timing_swap_start;
uint64_t arch_timing_swap_end;
uint64_t arch_timing_irq_start;
uint64_t arch_timing_irq_end;
uint64_t arch_timing_tick_start;
uint64_t arch_timing_tick_end;
uint64_t arch_timing_enter_user_mode_end;
/* location of the time stamps*/
uint32_t arch_timing_value_swap_end;
uint64_t arch_timing_value_swap_common;
uint64_t arch_timing_value_swap_temp;
#if defined(CONFIG_NRF_RTC_TIMER)
#include <nrfx.h>
/* To get current count of timer, first 1 need to be written into
* Capture Register and Current Count will be copied into corresponding
* current count register.
*/
#define TIMING_INFO_PRE_READ() (NRF_TIMER2->TASKS_CAPTURE[0] = 1)
#define TIMING_INFO_OS_GET_TIME() (NRF_TIMER2->CC[0])
#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
#define SUBTRACT_CLOCK_CYCLES(val) (val)
#elif defined(CONFIG_SOC_SERIES_MEC1501X)
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (B32TMR1_REGS->CNT)
#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
#define SUBTRACT_CLOCK_CYCLES(val) (val)
#elif defined(CONFIG_X86)
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (z_tsc_read())
#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
#define SUBTRACT_CLOCK_CYCLES(val) (val)
#elif defined(CONFIG_CPU_CORTEX_M)
#include <arch/arm/aarch32/cortex_m/cmsis.h>
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (SysTick->VAL)
#define SUBTRACT_CLOCK_CYCLES(val) (SysTick->LOAD - (uint32_t)val)
#elif defined(CONFIG_ARC)
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (z_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT))
#define SUBTRACT_CLOCK_CYCLES(val) ((uint32_t)val)
#elif defined(CONFIG_NIOS2)
#include "altera_avalon_timer_regs.h"
#define TIMING_INFO_PRE_READ() \
(IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10))
#define TIMING_INFO_OS_GET_TIME() (SUBTRACT_CLOCK_CYCLES(\
((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE))))
#define TIMING_INFO_GET_TIMER_VALUE() (\
((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((uint32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))
#define SUBTRACT_CLOCK_CYCLES(val) \
((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) \
<< 16 | \
(IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) \
- ((uint32_t)val))
#else
#define TIMING_INFO_PRE_READ()
#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
#define SUBTRACT_CLOCK_CYCLES(val) ((uint32_t)val)
#endif /* CONFIG_NRF_RTC_TIMER */
void read_timer_start_of_swap(void)
{
if (arch_timing_value_swap_end == 1U) {
TIMING_INFO_PRE_READ();
arch_timing_swap_start = (uint32_t) TIMING_INFO_OS_GET_TIME();
}
}
void read_timer_end_of_swap(void)
{
if (arch_timing_value_swap_end == 1U) {
TIMING_INFO_PRE_READ();
arch_timing_value_swap_end = 2U;
arch_timing_value_swap_common =
(uint64_t)TIMING_INFO_OS_GET_TIME();
}
}
/* ARM processors read current value of time through sysTick timer
* and nrf soc read it though timer
*/
void read_timer_start_of_isr(void)
{
TIMING_INFO_PRE_READ();
arch_timing_irq_start = (uint32_t) TIMING_INFO_GET_TIMER_VALUE();
}
void read_timer_end_of_isr(void)
{
TIMING_INFO_PRE_READ();
arch_timing_irq_end = (uint32_t) TIMING_INFO_GET_TIMER_VALUE();
}
void read_timer_start_of_tick_handler(void)
{
TIMING_INFO_PRE_READ();
arch_timing_tick_start = (uint32_t)TIMING_INFO_GET_TIMER_VALUE();
}
void read_timer_end_of_tick_handler(void)
{
TIMING_INFO_PRE_READ();
arch_timing_tick_end = (uint32_t) TIMING_INFO_GET_TIMER_VALUE();
}
void read_timer_end_of_userspace_enter(void)
{
TIMING_INFO_PRE_READ();
arch_timing_enter_user_mode_end = (uint32_t)TIMING_INFO_GET_TIMER_VALUE();
}

9
arch/nios2/core/irq_manage.c
View file

@ -80,11 +80,6 @@ void _enter_irq(uint32_t ipending)
{ {
int index; int index;
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_isr(void);
read_timer_start_of_isr();
#endif
_kernel.cpus[0].nested++; _kernel.cpus[0].nested++;
#ifdef CONFIG_IRQ_OFFLOAD #ifdef CONFIG_IRQ_OFFLOAD
@ -103,10 +98,6 @@ void _enter_irq(uint32_t ipending)
ite = &_sw_isr_table[index]; ite = &_sw_isr_table[index];
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_isr(void);
read_timer_end_of_isr();
#endif
ite->isr(ite->arg); ite->isr(ite->arg);
#ifdef CONFIG_TRACING_ISR #ifdef CONFIG_TRACING_ISR
sys_trace_isr_exit(); sys_trace_isr_exit();

12
arch/nios2/core/swap.S
View file

@ -21,7 +21,7 @@ GTEXT(_k_neg_eagain)
*/ */
SECTION_FUNC(exception.other, arch_swap) SECTION_FUNC(exception.other, arch_swap)
#if defined(CONFIG_EXECUTION_BENCHMARKING) || defined(CONFIG_TRACING) #if defined(CONFIG_TRACING)
/* Get a reference to _kernel in r10 */ /* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel) movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel) ori r10, r10, %lo(_kernel)
@ -34,11 +34,7 @@ SECTION_FUNC(exception.other, arch_swap)
stw ra, _thread_offset_to_ra(r11) stw ra, _thread_offset_to_ra(r11)
stw sp, _thread_offset_to_sp(r11) stw sp, _thread_offset_to_sp(r11)
#if CONFIG_TRACING
call sys_trace_thread_switched_out call sys_trace_thread_switched_out
#elif CONFIG_EXECUTION_BENCHMARKING
call read_timer_start_of_swap
#endif
/* Get a reference to _kernel in r10 */ /* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel) movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel) ori r10, r10, %lo(_kernel)
@ -139,7 +135,7 @@ no_unlock:
wrctl status, r3 wrctl status, r3
#endif #endif
#if defined(CONFIG_EXECUTION_BENCHMARKING) || defined(CONFIG_TRACING) #if defined(CONFIG_TRACING)
/* Get a reference to _kernel in r10 */ /* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel) movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel) ori r10, r10, %lo(_kernel)
@ -151,11 +147,7 @@ no_unlock:
stw ra, _thread_offset_to_ra(r11) stw ra, _thread_offset_to_ra(r11)
stw sp, _thread_offset_to_sp(r11) stw sp, _thread_offset_to_sp(r11)
#if CONFIG_TRACING
call sys_trace_thread_switched_in call sys_trace_thread_switched_in
#elif CONFIG_EXECUTION_BENCHMARKING
call read_timer_end_of_swap
#endif
/* Get a reference to _kernel in r10 */ /* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel) movhi r10, %hi(_kernel)

79
arch/riscv/core/isr.S
View file

@ -171,10 +171,6 @@ skip_store_fp_caller_saved:
jal ra, __soc_save_context jal ra, __soc_save_context
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */ #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
#ifdef CONFIG_EXECUTION_BENCHMARKING
call read_timer_start_of_isr
#endif
/* /*
* Check if exception is the result of an interrupt or not. * Check if exception is the result of an interrupt or not.
* (SOC dependent). Following the RISC-V architecture spec, the MSB * (SOC dependent). Following the RISC-V architecture spec, the MSB
@ -321,15 +317,6 @@ call_irq:
/* Load ISR function address in register t1 */ /* Load ISR function address in register t1 */
RV_OP_LOADREG t1, RV_REGSIZE(t0) RV_OP_LOADREG t1, RV_REGSIZE(t0)
#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -16
RV_OP_STOREREG a0, 0x00(sp)
RV_OP_STOREREG t1, RV_REGSIZE(sp)
call read_timer_end_of_isr
RV_OP_LOADREG t1, RV_REGSIZE(sp)
RV_OP_LOADREG a0, 0x00(sp)
addi sp, sp, 16
#endif
/* Call ISR function */ /* Call ISR function */
jalr ra, t1 jalr ra, t1
@ -460,72 +447,6 @@ skip_store_fp_callee_saved:
skip_load_fp_callee_saved: skip_load_fp_callee_saved:
#endif #endif
#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -__z_arch_esf_t_SIZEOF
RV_OP_STOREREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_STOREREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_STOREREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_STOREREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_STOREREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_STOREREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_STOREREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_STOREREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_STOREREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_STOREREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_STOREREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_STOREREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_STOREREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_STOREREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_STOREREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_STOREREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
/* Assess whether floating-point registers need to be saved. */
RV_OP_LOADREG t2, _thread_offset_to_user_options(sp)
andi t2, t2, K_FP_REGS
RV_OP_STOREREG t2, __z_arch_esf_t_fp_state_OFFSET(sp)
beqz t2, skip_store_fp_caller_saved_benchmark
STORE_FP_CALLER_SAVED(sp)
skip_store_fp_caller_saved_benchmark:
#endif
call read_timer_end_of_swap
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
/* Determine if we need to restore floating-point registers. */
RV_OP_LOADREG t2, __z_arch_esf_t_fp_state_OFFSET(sp)
beqz t2, skip_load_fp_caller_saved_benchmark
LOAD_FP_CALLER_SAVED(sp)
skip_load_fp_caller_saved_benchmark:
#endif
RV_OP_LOADREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_LOADREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_LOADREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_LOADREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_LOADREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_LOADREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_LOADREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_LOADREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_LOADREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_LOADREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_LOADREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_LOADREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_LOADREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_LOADREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_LOADREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_LOADREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_LOADREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_LOADREG a7, __z_arch_esf_t_a7_OFFSET(sp)
/* Release stack space */
addi sp, sp, __z_arch_esf_t_SIZEOF
#endif
#if CONFIG_TRACING #if CONFIG_TRACING
call sys_trace_thread_switched_in call sys_trace_thread_switched_in
#endif #endif

46
arch/riscv/core/swap.S
View file

@ -24,52 +24,6 @@ GTEXT(z_thread_entry_wrapper)
SECTION_FUNC(exception.other, arch_swap) SECTION_FUNC(exception.other, arch_swap)
/* Make a system call to perform context switch */ /* Make a system call to perform context switch */
#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -__z_arch_esf_t_SIZEOF
RV_OP_STOREREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_STOREREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_STOREREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_STOREREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_STOREREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_STOREREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_STOREREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_STOREREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_STOREREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_STOREREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_STOREREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_STOREREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_STOREREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_STOREREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_STOREREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_STOREREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
call read_timer_start_of_swap
RV_OP_LOADREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_LOADREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_LOADREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_LOADREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_LOADREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_LOADREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_LOADREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_LOADREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_LOADREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_LOADREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_LOADREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_LOADREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_LOADREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_LOADREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_LOADREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_LOADREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_LOADREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_LOADREG a7, __z_arch_esf_t_a7_OFFSET(sp)
/* Release stack space */
addi sp, sp, __z_arch_esf_t_SIZEOF
#endif
ecall ecall
/* /*

24
arch/x86/core/ia32/intstub.S
View file

@ -35,7 +35,6 @@
GTEXT(z_sys_power_save_idle_exit) GTEXT(z_sys_power_save_idle_exit)
#endif #endif
/** /**
* *
* @brief Inform the kernel of an interrupt * @brief Inform the kernel of an interrupt
@ -79,15 +78,6 @@ SECTION_FUNC(TEXT, _interrupt_enter)
* 0 isr <-- stack pointer * 0 isr <-- stack pointer
*/ */
#ifdef CONFIG_EXECUTION_BENCHMARKING
pushl %eax
pushl %edx
rdtsc
mov %eax, arch_timing_irq_start
mov %edx, arch_timing_irq_start+4
pop %edx
pop %eax
#endif
/* /*
* The gen_idt tool creates an interrupt-gate descriptor for * The gen_idt tool creates an interrupt-gate descriptor for
* all connections. The processor will automatically clear the IF * all connections. The processor will automatically clear the IF
@ -166,20 +156,6 @@ alreadyOnIntStack:
push %eax /* interrupt handler argument */ push %eax /* interrupt handler argument */
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Save the eax and edx registers before reading the time stamp
* once done pop the values
*/
pushl %eax
pushl %edx
rdtsc
mov %eax,arch_timing_irq_end
mov %edx,arch_timing_irq_end+4
pop %edx
pop %eax
#endif
#if defined(CONFIG_TRACING_ISR) #if defined(CONFIG_TRACING_ISR)
/* Save these as we are using to keep track of isr and isr_param */ /* Save these as we are using to keep track of isr and isr_param */
pushl %eax pushl %eax

32
arch/x86/core/ia32/swap.S
View file

@ -65,30 +65,7 @@
* unsigned int arch_swap (unsigned int eflags); * unsigned int arch_swap (unsigned int eflags);
*/ */
.macro read_tsc var_name
push %eax
push %edx
rdtsc
mov %eax,\var_name
mov %edx,\var_name+4
pop %edx
pop %eax
.endm
SECTION_FUNC(TEXT, arch_swap) SECTION_FUNC(TEXT, arch_swap)
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Save the eax and edx registers before reading the time stamp
* once done pop the values.
*/
push %eax
push %edx
rdtsc
mov %eax,arch_timing_swap_start
mov %edx,arch_timing_swap_start+4
pop %edx
pop %eax
#endif
#if defined(CONFIG_TRACING) #if defined(CONFIG_TRACING)
pushl %eax pushl %eax
call sys_trace_thread_switched_out call sys_trace_thread_switched_out
@ -355,15 +332,6 @@ CROHandlingDone:
pushl 4(%esp) pushl 4(%esp)
popfl popfl
#ifdef CONFIG_EXECUTION_BENCHMARKING
cmp $0x1,arch_timing_value_swap_end
jne time_read_not_needed
movw $0x2,arch_timing_value_swap_end
read_tsc arch_timing_value_swap_common
pushl arch_timing_swap_start
popl arch_timing_value_swap_temp
time_read_not_needed:
#endif
#if defined(CONFIG_TRACING) #if defined(CONFIG_TRACING)
pushl %eax pushl %eax
call sys_trace_thread_switched_in call sys_trace_thread_switched_in

13
arch/x86/core/ia32/userspace.S
View file

@ -374,18 +374,5 @@ SECTION_FUNC(TEXT, z_x86_userspace_enter)
push $USER_CODE_SEG /* CS */ push $USER_CODE_SEG /* CS */
push $z_thread_entry /* EIP */ push $z_thread_entry /* EIP */
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Save the eax and edx registers before reading the time stamp
* once done pop the values.
*/
push %eax
push %edx
rdtsc
mov %eax,arch_timing_enter_user_mode_end
mov %edx,arch_timing_enter_user_mode_end+4
pop %edx
pop %eax
#endif
/* We will land in z_thread_entry() in user mode after this */ /* We will land in z_thread_entry() in user mode after this */
KPTI_IRET_USER KPTI_IRET_USER

33
arch/x86/core/intel64/locore.S
View file

@ -3,6 +3,7 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <toolchain.h>
#include <arch/x86/multiboot.h> #include <arch/x86/multiboot.h>
#include <sys/util.h> #include <sys/util.h>
#include <arch/x86/msr.h> #include <arch/x86/msr.h>
@ -12,16 +13,6 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <sys/mem_manage.h> #include <sys/mem_manage.h>
.macro read_tsc var_name
push %rax
push %rdx
rdtsc
mov %eax,\var_name
mov %edx,\var_name+4
pop %rdx
pop %rax
.endm
/* /*
* Definitions/macros for enabling paging * Definitions/macros for enabling paging
*/ */
@ -287,10 +278,6 @@ mxcsr: .long X86_MXCSR_SANE
.globl z_x86_switch .globl z_x86_switch
z_x86_switch: z_x86_switch:
#ifdef CONFIG_EXECUTION_BENCHMARKING
read_tsc arch_timing_swap_start
#endif
/* RSI contains the switch_handle field to which we are /* RSI contains the switch_handle field to which we are
* notionally supposed to store. Offset it to get back to the * notionally supposed to store. Offset it to get back to the
* thread handle instead. * thread handle instead.
@ -415,16 +402,6 @@ __resume:
lfence lfence
#endif /* CONFIG_X86_BOUNDS_CHECK_BYPASS_MITIGATION */ #endif /* CONFIG_X86_BOUNDS_CHECK_BYPASS_MITIGATION */
#ifdef CONFIG_EXECUTION_BENCHMARKING
cmp $0x1,arch_timing_value_swap_end
jne time_read_not_needed
movw $0x2,arch_timing_value_swap_end
read_tsc arch_timing_value_swap_common
pushq arch_timing_swap_start
popq arch_timing_value_swap_temp
time_read_not_needed:
#endif
iretq iretq
@ -592,10 +569,6 @@ EXCEPT(Z_X86_OOPS_VECTOR);
.globl x86_irq_args /* .. for these definitions */ .globl x86_irq_args /* .. for these definitions */
irq: irq:
#ifdef CONFIG_EXECUTION_BENCHMARKING
read_tsc arch_timing_irq_start
#endif
pushq %rsi pushq %rsi
#ifdef CONFIG_USERSPACE #ifdef CONFIG_USERSPACE
@ -711,10 +684,6 @@ irq_enter_unnested: /* Not nested: dump state to thread struct for __resume */
#endif #endif
irq_dispatch: irq_dispatch:
#ifdef CONFIG_EXECUTION_BENCHMARKING
read_tsc arch_timing_irq_end
#endif
movq x86_irq_funcs(,%rcx,8), %rbx movq x86_irq_funcs(,%rcx,8), %rbx
movq x86_irq_args(,%rcx,8), %rdi movq x86_irq_args(,%rcx,8), %rdi
call *%rbx call *%rbx

14
arch/x86/core/intel64/userspace.S
View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include <toolchain.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <offsets_short.h> #include <offsets_short.h>
#include <syscall.h> #include <syscall.h>
@ -325,19 +326,6 @@ z_x86_userspace_enter:
cli cli
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Save the eax and edx registers before reading the time stamp
* once done pop the values.
*/
push %rax
push %rdx
rdtsc
mov %eax,arch_timing_enter_user_mode_end
mov %edx,arch_timing_enter_user_mode_end+4
pop %rdx
pop %rax
#endif
#ifdef CONFIG_X86_KPTI #ifdef CONFIG_X86_KPTI
/* Switch to thread's page table. We have free registers so no need /* Switch to thread's page table. We have free registers so no need
* to involve the trampoline stack. * to involve the trampoline stack.

3
arch/xtensa/core/xtensa-asm2-util.S
View file

@ -225,9 +225,6 @@ xtensa_switch:
*/ */
l32i a1, a2, BSA_A2_OFF l32i a1, a2, BSA_A2_OFF
#ifdef CONFIG_EXECUTION_BENCHMARKING
call4 read_timer_end_of_swap
#endif
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
call4 sys_trace_thread_switched_in call4 sys_trace_thread_switched_in
#endif #endif

1
doc/zephyr.doxyfile.in
View file

@ -1968,7 +1968,6 @@ PREDEFINED = "CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT" \
"CONFIG_DEVICE_POWER_MANAGEMENT" \ "CONFIG_DEVICE_POWER_MANAGEMENT" \
"CONFIG_DEVICE_IDLE_PM" \ "CONFIG_DEVICE_IDLE_PM" \
"CONFIG_ERRNO" \ "CONFIG_ERRNO" \
"CONFIG_EXECUTION_BENCHMARKING" \
"CONFIG_FLASH_JESD216_API" \ "CONFIG_FLASH_JESD216_API" \
"CONFIG_FLASH_PAGE_LAYOUT" \ "CONFIG_FLASH_PAGE_LAYOUT" \
"CONFIG_FPU" \ "CONFIG_FPU" \

10
drivers/timer/altera_avalon_timer_hal.c
View file

@ -23,22 +23,12 @@ static void timer_irq_handler(const void *unused)
{ {
ARG_UNUSED(unused); ARG_UNUSED(unused);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_tick_handler(void);
read_timer_start_of_tick_handler();
#endif
accumulated_cycle_count += k_ticks_to_cyc_floor32(1); accumulated_cycle_count += k_ticks_to_cyc_floor32(1);
/* Clear the interrupt */ /* Clear the interrupt */
alt_handle_irq((void *)TIMER_0_BASE, TIMER_0_IRQ); alt_handle_irq((void *)TIMER_0_BASE, TIMER_0_IRQ);
z_clock_announce(_sys_idle_elapsed_ticks); z_clock_announce(_sys_idle_elapsed_ticks);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_tick_handler(void);
read_timer_end_of_tick_handler();
#endif
} }
int z_clock_driver_init(const struct device *device) int z_clock_driver_init(const struct device *device)

10
drivers/timer/hpet.c
View file

@ -50,11 +50,6 @@ static void hpet_isr(const void *arg)
{ {
ARG_UNUSED(arg); ARG_UNUSED(arg);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_tick_handler(void);
read_timer_start_of_tick_handler();
#endif
k_spinlock_key_t key = k_spin_lock(&lock); k_spinlock_key_t key = k_spin_lock(&lock);
uint32_t now = MAIN_COUNTER_REG; uint32_t now = MAIN_COUNTER_REG;
@ -96,11 +91,6 @@ static void hpet_isr(const void *arg)
k_spin_unlock(&lock, key); k_spin_unlock(&lock, key);
z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1); z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_tick_handler(void);
read_timer_end_of_tick_handler();
#endif
} }
static void set_timer0_irq(unsigned int irq) static void set_timer0_irq(unsigned int irq)

6
drivers/timer/loapic_timer.c
View file

@ -201,9 +201,6 @@ static inline void program_max_cycles(void)
void timer_int_handler(const void *unused /* parameter is not used */ void timer_int_handler(const void *unused /* parameter is not used */
) )
{ {
#ifdef CONFIG_EXECUTION_BENCHMARKING
arch_timing_tick_start = z_tsc_read();
#endif
ARG_UNUSED(unused); ARG_UNUSED(unused);
#if defined(CONFIG_TICKLESS_KERNEL) #if defined(CONFIG_TICKLESS_KERNEL)
@ -281,9 +278,6 @@ void timer_int_handler(const void *unused /* parameter is not used */
z_clock_announce(_sys_idle_elapsed_ticks); z_clock_announce(_sys_idle_elapsed_ticks);
#endif /*CONFIG_TICKLESS_IDLE*/ #endif /*CONFIG_TICKLESS_IDLE*/
#endif #endif
#ifdef CONFIG_EXECUTION_BENCHMARKING
arch_timing_tick_end = z_tsc_read();
#endif /* CONFIG_EXECUTION_BENCHMARKING */
} }
#ifdef CONFIG_TICKLESS_KERNEL #ifdef CONFIG_TICKLESS_KERNEL

10
drivers/timer/mchp_xec_rtos_timer.c
View file

@ -217,11 +217,6 @@ static void xec_rtos_timer_isr(const void *arg)
{ {
ARG_UNUSED(arg); ARG_UNUSED(arg);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_tick_handler(void);
read_timer_start_of_tick_handler();
#endif
uint32_t cycles; uint32_t cycles;
int32_t ticks; int32_t ticks;
@ -248,11 +243,6 @@ static void xec_rtos_timer_isr(const void *arg)
k_spin_unlock(&lock, key); k_spin_unlock(&lock, key);
z_clock_announce(ticks); z_clock_announce(ticks);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_tick_handler(void);
read_timer_end_of_tick_handler();
#endif
} }
#else #else

1
include/arch/x86/ia32/asm.h
View file

@ -24,6 +24,7 @@ GTEXT(z_x86_trampoline_to_kernel)
#define KPTI_IRET iret #define KPTI_IRET iret
#define KPTI_IRET_USER iret #define KPTI_IRET_USER iret
#endif /* CONFIG_X86_KPTI */ #endif /* CONFIG_X86_KPTI */
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_ASM_H_ */ #endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_ASM_H_ */

21
include/sys/arch_interface.h
View file

@ -693,27 +693,6 @@ size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err);
/** @} */ /** @} */
/**
* @defgroup arch-benchmarking Architecture-specific benchmarking globals
* @ingroup arch-interface
* @{
*/
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern uint64_t arch_timing_swap_start;
extern uint64_t arch_timing_swap_end;
extern uint64_t arch_timing_irq_start;
extern uint64_t arch_timing_irq_end;
extern uint64_t arch_timing_tick_start;
extern uint64_t arch_timing_tick_end;
extern uint64_t arch_timing_user_mode_end;
extern uint32_t arch_timing_value_swap_end;
extern uint64_t arch_timing_value_swap_common;
extern uint64_t arch_timing_value_swap_temp;
#endif /* CONFIG_EXECUTION_BENCHMARKING */
/** @} */
/** /**
* @defgroup arch-gdbstub Architecture-specific gdbstub APIs * @defgroup arch-gdbstub Architecture-specific gdbstub APIs
* @ingroup arch-interface * @ingroup arch-interface

9
kernel/Kconfig
View file

@ -314,15 +314,6 @@ config BOOT_DELAY
achieved by waiting for DCD on the serial port--however, not achieved by waiting for DCD on the serial port--however, not
all serial ports have DCD. all serial ports have DCD.
config EXECUTION_BENCHMARKING
bool "Timing metrics"
select TIMING_FUNCTIONS
help
This option enables the tracking of various times inside the kernel
the exact set of metrics being tracked is board-dependent.
All timing measurements are enabled for X86 and ARM based architectures.
In other architectures only a subset is enabled.
config THREAD_MONITOR config THREAD_MONITOR
bool "Thread monitoring [EXPERIMENTAL]" bool "Thread monitoring [EXPERIMENTAL]"
help help

5
kernel/include/kswap.h
View file

@ -64,11 +64,6 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key,
ARG_UNUSED(lock); ARG_UNUSED(lock);
struct k_thread *new_thread, *old_thread; struct k_thread *new_thread, *old_thread;
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_swap(void);
read_timer_start_of_swap();
#endif
old_thread = _current; old_thread = _current;
z_check_stack_sentinel(); z_check_stack_sentinel();

1
scripts/kconfig/hardened.csv
View file

@ -3,7 +3,6 @@ INIT_STACKS,n
KERNEL_DEBUG,n KERNEL_DEBUG,n
BOOT_BANNER,n BOOT_BANNER,n
BOOT_DELAY,0 BOOT_DELAY,0
EXECUTION_BENCHMARKING,n
THREAD_MONITOR,n THREAD_MONITOR,n
THREAD_NAME,n THREAD_NAME,n
STACK_CANARIES,y STACK_CANARIES,y

1 HW_STACK_PROTECTION y
3 KERNEL_DEBUG n
4 BOOT_BANNER n
5 BOOT_DELAY 0
EXECUTION_BENCHMARKING n
6 THREAD_MONITOR n
7 THREAD_NAME n
8 STACK_CANARIES y