mbox: Add NXP MU as a MBOX device
Add a MBOX driver wrapper around the NXP MU, simular to the existing wrapper around the NXP S32 MRU. This allows Zephyr IPC to work based on the MU, on a number of NXP boards. Also update the SHA of NXP HAL to enable the Kconfig for this driver. Signed-off-by: Yicheng Li <yichengli@google.com>
This commit is contained in:
Yicheng Li
Carles Cufí
parent
f2069530ee
commit
6ead139b4b
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@ -459,6 +459,10 @@ zephyr_udc0: &usbhs {
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status = "okay";
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};
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&mbox {
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status = "okay";
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};
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/* Disable this node if not using USB and need another MPU region */
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&sram1 {
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status = "okay";
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@ -7,4 +7,5 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_USERSPACE mbox_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_NRFX_IPC mbox_nrfx_ipc.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_S32_MRU mbox_nxp_s32_mru.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_IMX_MU mbox_nxp_imx_mu.c)
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zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c)
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@ -13,6 +13,7 @@ if MBOX
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# overridden (by defining symbols in multiple locations)
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source "drivers/mbox/Kconfig.nrfx"
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source "drivers/mbox/Kconfig.nxp_s32"
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source "drivers/mbox/Kconfig.nxp_imx"
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source "drivers/mbox/Kconfig.andes"
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config MBOX_INIT_PRIORITY
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9
drivers/mbox/Kconfig.nxp_imx
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9
drivers/mbox/Kconfig.nxp_imx
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@ -0,0 +1,9 @@
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# Copyright 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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config MBOX_NXP_IMX_MU
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bool "NXP i.MX Message Unit (MU) driver"
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default y
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depends on DT_HAS_NXP_MBOX_IMX_MU_ENABLED
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help
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Driver for NXP i.MX Message Unit.
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179
drivers/mbox/mbox_nxp_imx_mu.c
Normal file
179
drivers/mbox/mbox_nxp_imx_mu.c
Normal file
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@ -0,0 +1,179 @@
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/*
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* Wrapper of the i.MX Message Unit driver into Zephyr's MBOX model.
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/mbox.h>
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#include <zephyr/sys/util_macro.h>
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#include <fsl_mu.h>
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#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(nxp_mbox_imx_mu);
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#define DT_DRV_COMPAT nxp_mbox_imx_mu
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#define MU_MAX_CHANNELS 4
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#define MU_MBOX_SIZE sizeof(uint32_t)
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struct nxp_imx_mu_data {
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mbox_callback_t cb[MU_MAX_CHANNELS];
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void *user_data[MU_MAX_CHANNELS];
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};
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struct nxp_imx_mu_config {
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MU_Type *base;
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};
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static int nxp_imx_mu_send(const struct device *dev, uint32_t channel,
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const struct mbox_msg *msg)
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{
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uint32_t __aligned(4) data32;
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const struct nxp_imx_mu_config *cfg = dev->config;
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if (channel >= MU_MAX_CHANNELS) {
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return -EINVAL;
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}
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/* Signalling mode. */
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if (msg == NULL) {
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return MU_TriggerInterrupts(
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cfg->base, kMU_GenInt0InterruptTrigger);
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}
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/* Data transfer mode. */
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if (msg->size != MU_MBOX_SIZE) {
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/* We can only send this many bytes at a time. */
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return -EMSGSIZE;
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}
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/* memcpy to avoid issues when msg->data is not word-aligned. */
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memcpy(&data32, msg->data, msg->size);
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MU_SendMsg(cfg->base, channel, data32);
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return 0;
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}
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static int nxp_imx_mu_register_callback(const struct device *dev, uint32_t channel,
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mbox_callback_t cb, void *user_data)
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{
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struct nxp_imx_mu_data *data = dev->data;
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if (channel >= MU_MAX_CHANNELS) {
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return -EINVAL;
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}
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data->cb[channel] = cb;
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data->user_data[channel] = user_data;
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return 0;
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}
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static int nxp_imx_mu_mtu_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MU_MBOX_SIZE;
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}
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static uint32_t nxp_imx_mu_max_channels_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MU_MAX_CHANNELS;
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}
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static int nxp_imx_mu_set_enabled(const struct device *dev, uint32_t channel,
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bool enable)
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{
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struct nxp_imx_mu_data *data = dev->data;
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const struct nxp_imx_mu_config *cfg = dev->config;
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if (channel >= MU_MAX_CHANNELS) {
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return -EINVAL;
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}
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if (enable) {
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if (data->cb[channel] == NULL) {
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LOG_WRN("Enabling channel without a registered callback");
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}
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MU_EnableInterrupts(cfg->base,
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kMU_GenInt0InterruptEnable | kMU_GenInt1InterruptEnable |
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kMU_GenInt2InterruptEnable | kMU_GenInt3InterruptEnable |
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kMU_Rx0FullInterruptEnable | kMU_Rx1FullInterruptEnable |
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kMU_Rx2FullInterruptEnable | kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(cfg->base,
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kMU_GenInt0InterruptEnable | kMU_GenInt1InterruptEnable |
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kMU_GenInt2InterruptEnable | kMU_GenInt3InterruptEnable |
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kMU_Rx0FullInterruptEnable | kMU_Rx1FullInterruptEnable |
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kMU_Rx2FullInterruptEnable | kMU_Rx3FullInterruptEnable);
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}
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return 0;
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}
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static const struct mbox_driver_api nxp_imx_mu_driver_api = {
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.send = nxp_imx_mu_send,
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.register_callback = nxp_imx_mu_register_callback,
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.mtu_get = nxp_imx_mu_mtu_get,
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.max_channels_get = nxp_imx_mu_max_channels_get,
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.set_enabled = nxp_imx_mu_set_enabled,
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};
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#define MU_INSTANCE_DEFINE(idx) \
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static struct nxp_imx_mu_data nxp_imx_mu_##idx##_data; \
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static struct nxp_imx_mu_config nxp_imx_mu_##idx##_config = { \
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.base = (MU_Type *)DT_INST_REG_ADDR(idx), \
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}; \
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\
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void MU_##idx##_IRQHandler(void); \
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static int nxp_imx_mu_##idx##_init(const struct device *dev) \
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{ \
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ARG_UNUSED(dev); \
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MU_Init(nxp_imx_mu_##idx##_config.base); \
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IRQ_CONNECT(DT_INST_IRQN(idx), \
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DT_INST_IRQ(idx, priority), \
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MU_##idx##_IRQHandler, \
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NULL, \
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0); \
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irq_enable(DT_INST_IRQN(idx)); \
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return 0; \
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} \
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DEVICE_DT_INST_DEFINE(idx, nxp_imx_mu_##idx##_init, NULL, \
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&nxp_imx_mu_##idx##_data, &nxp_imx_mu_##idx##_config, \
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POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, \
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&nxp_imx_mu_driver_api)
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#define MU_IRQ_HANDLER(idx) \
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static uint32_t mu_##idx##_received_data; \
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void MU_##idx##_IRQHandler(void) \
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{ \
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const struct device *dev = DEVICE_DT_INST_GET(idx); \
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const struct nxp_imx_mu_data *data = dev->data; \
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const struct nxp_imx_mu_config *config = dev->config; \
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int channel = 0; \
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struct mbox_msg msg; \
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struct mbox_msg *callback_msg_ptr = NULL; \
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uint32_t flag = MU_GetStatusFlags(config->base); \
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\
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if ((flag & kMU_Rx0FullFlag) == kMU_Rx0FullFlag) { \
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mu_##idx##_received_data = \
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MU_ReceiveMsgNonBlocking(config->base, 0); \
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msg.data = (const void *)&mu_##idx##_received_data; \
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msg.size = MU_MBOX_SIZE; \
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callback_msg_ptr = &msg; \
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} else if ((flag & kMU_GenInt0Flag) == kMU_GenInt0Flag) { \
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MU_ClearStatusFlags(config->base, kMU_GenInt0Flag); \
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callback_msg_ptr = NULL; \
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} \
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\
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if (data->cb[channel]) { \
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data->cb[channel](dev, channel, \
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data->user_data[channel], \
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callback_msg_ptr); \
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} \
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}
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#define MU_INST(idx) \
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MU_INSTANCE_DEFINE(idx); \
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MU_IRQ_HANDLER(idx);
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DT_INST_FOREACH_STATUS_OKAY(MU_INST)
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@ -546,6 +546,15 @@
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#address-cells = <3>;
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#size-cells = <0>;
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};
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mbox:mbox@110000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x110000 0x100>;
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interrupts = <34 0>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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};
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&flexspi {
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29
dts/bindings/mbox/nxp,mbox-imx-mu.yaml
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29
dts/bindings/mbox/nxp,mbox-imx-mu.yaml
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@ -0,0 +1,29 @@
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description: |
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NXP i.MX Message Unit as Zephyr MBOX
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compatible: "nxp,mbox-imx-mu"
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include: [base.yaml, mailbox-controller.yaml]
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properties:
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interrupts:
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required: true
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rx-channels:
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type: int
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enum: [1, 2, 3, 4]
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description: |
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Number of receive channels enabled on this instance.
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Setting this value to N, will enable channels 0 to N-1, consecutively.
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It should be set by the receiver core coupled with this MU instance.
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For example, if receiver A wants to Rx on channels 0 to 3, then A must
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set rx-channels of muA as follows:
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mruA {
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rx-channels = <4>;
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status = "okay";
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};
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mbox-cells:
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- channel
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@ -12,6 +12,8 @@ if("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")
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set(BOARD_REMOTE "nrf5340dk_nrf5340_cpunet")
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elseif("${BOARD}" STREQUAL "adp_xc7k_ae350")
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set(BOARD_REMOTE "adp_xc7k_ae350")
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elseif("${BOARD}" STREQUAL "mimxrt595_evk_cm33")
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set(BOARD_REMOTE "nrf5340dk_nrf5340_cpunet")
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else()
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message(FATAL_ERROR "${BOARD} is not supported for this sample")
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endif()
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1
samples/drivers/mbox/boards/mimxrt595_evk_cm33.conf
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1
samples/drivers/mbox/boards/mimxrt595_evk_cm33.conf
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@ -0,0 +1 @@
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CONFIG_MBOX_NXP_IMX_MU=y
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@ -2,7 +2,10 @@ sample:
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name: MBOX IPC sample
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tests:
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sample.drivers.mbox:
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platform_allow: nrf5340dk_nrf5340_cpuapp adp_xc7k_ae350
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platform_allow:
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- nrf5340dk_nrf5340_cpuapp
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- adp_xc7k_ae350
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- mimxrt595_evk_cm33
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integration_platforms:
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- nrf5340dk_nrf5340_cpuapp
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tags: mbox
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