drivers: add CC13xx / CC26xx I2C driver
Add I2C driver for the TI CC13xx / CC26xx series SoCs. Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
This commit is contained in:
Brett Witherspoon
Anas Nashif
parent
a5e929ab98
commit
6eb0cb0d85
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@ -3,6 +3,7 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_I2C_BITBANG i2c_bitbang.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_CC13XX_CC26XX i2c_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_CC32XX i2c_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_ESP32 i2c_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_GPIO i2c_gpio.c)
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@ -18,6 +18,7 @@ if I2C
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# Include these first so that any properties (e.g. defaults) below can be
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# overriden (by defining symbols in multiple locations)
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source "drivers/i2c/Kconfig.cc13xx_cc26xx"
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source "drivers/i2c/Kconfig.dw"
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source "drivers/i2c/Kconfig.esp32"
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source "drivers/i2c/slave/Kconfig"
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12
drivers/i2c/Kconfig.cc13xx_cc26xx
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12
drivers/i2c/Kconfig.cc13xx_cc26xx
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@ -0,0 +1,12 @@
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#
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# Copyright (c) 2019 Brett Witherspoon
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config I2C_CC13XX_CC26XX
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bool "TI SimpleLink CC13xx / CC26xx I2C driver"
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depends on SOC_SERIES_CC13X2_CC26X2
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select HAS_DTS_I2C
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help
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Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series.
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337
drivers/i2c/i2c_cc13xx_cc26xx.c
Normal file
337
drivers/i2c/i2c_cc13xx_cc26xx.c
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@ -0,0 +1,337 @@
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/*
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* Copyright (c) 2019 Brett Witherspoon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <i2c.h>
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_cc13xx_cc26xx);
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#include <driverlib/i2c.h>
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#include <driverlib/ioc.h>
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#include <driverlib/prcm.h>
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#include "i2c-priv.h"
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DEVICE_DECLARE(i2c_cc13xx_cc26xx);
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struct i2c_cc13xx_cc26xx_data {
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struct k_sem lock;
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struct k_sem complete;
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volatile u32_t error;
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};
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struct i2c_cc13xx_cc26xx_config {
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u32_t base;
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u32_t scl_pin;
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u32_t sda_pin;
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};
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static inline struct i2c_cc13xx_cc26xx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct i2c_cc13xx_cc26xx_config *
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get_dev_config(struct device *dev)
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{
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return dev->config->config_info;
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}
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static int i2c_cc13xx_cc26xx_transmit(struct device *dev, const u8_t *buf,
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u32_t len, u16_t addr)
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{
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const u32_t base = get_dev_config(dev)->base;
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struct i2c_cc13xx_cc26xx_data *data = get_dev_data(dev);
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/* Sending address without data is not supported */
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if (len == 0) {
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return -EIO;
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}
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I2CMasterSlaveAddrSet(base, addr, false);
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/* The following assumes a single master. Use I2CMasterBusBusy() if
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* wanting to implement multiple master support.
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*/
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/* Single transmission */
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if (len == 1) {
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I2CMasterDataPut(base, *buf);
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I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_SEND);
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k_sem_take(&data->complete, K_FOREVER);
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return data->error == I2C_MASTER_ERR_NONE ? 0 : -EIO;
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}
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/* Burst transmission */
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I2CMasterDataPut(base, buf[0]);
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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goto send_error_stop;
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}
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for (int i = 1; i < len - 1; i++) {
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I2CMasterDataPut(base, buf[i]);
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_CONT);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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goto send_error_stop;
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}
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}
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I2CMasterDataPut(base, buf[len - 1]);
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_FINISH);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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return -EIO;
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}
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return 0;
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send_error_stop:
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
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return -EIO;
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}
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static int i2c_cc13xx_cc26xx_receive(struct device *dev, u8_t *buf, u32_t len,
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u16_t addr)
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{
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const u32_t base = get_dev_config(dev)->base;
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struct i2c_cc13xx_cc26xx_data *data = get_dev_data(dev);
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/* Sending address without data is not supported */
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if (len == 0) {
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return -EIO;
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}
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I2CMasterSlaveAddrSet(base, addr, true);
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/* The following assumes a single master. Use I2CMasterBusBusy() if
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* wanting to implement multiple master support.
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*/
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/* Single receive */
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if (len == 1) {
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I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_RECEIVE);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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return -EIO;
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}
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*buf = I2CMasterDataGet(base);
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return 0;
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}
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/* Burst receive */
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_START);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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goto recv_error_stop;
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}
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buf[0] = I2CMasterDataGet(base);
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for (int i = 1; i < len - 1; i++) {
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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goto recv_error_stop;
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}
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buf[i] = I2CMasterDataGet(base);
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}
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
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k_sem_take(&data->complete, K_FOREVER);
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if (data->error != I2C_MASTER_ERR_NONE) {
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return -EIO;
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}
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buf[len - 1] = I2CMasterDataGet(base);
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return 0;
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recv_error_stop:
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I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP);
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return -EIO;
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}
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static int i2c_cc13xx_cc26xx_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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int ret = 0;
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if (num_msgs == 0) {
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return 0;
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}
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k_sem_take(&get_dev_data(dev)->lock, K_FOREVER);
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for (int i = 0; i < num_msgs; i++) {
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/* Not supported by hardware */
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if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
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ret = -EIO;
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break;
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}
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if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
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ret = i2c_cc13xx_cc26xx_transmit(dev, msgs[i].buf,
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msgs[i].len, addr);
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} else {
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ret = i2c_cc13xx_cc26xx_receive(dev, msgs[i].buf,
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msgs[i].len, addr);
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}
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if (ret) {
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break;
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}
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}
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k_sem_give(&get_dev_data(dev)->lock);
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return ret;
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}
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static int i2c_cc13xx_cc26xx_configure(struct device *dev, u32_t dev_config)
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{
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bool fast;
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switch (I2C_SPEED_GET(dev_config)) {
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case I2C_SPEED_STANDARD:
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fast = false;
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break;
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case I2C_SPEED_FAST:
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fast = true;
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break;
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default:
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LOG_ERR("Unsupported speed");
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return -EIO;
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}
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/* Support for slave mode has not been implemented */
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if (!(dev_config & I2C_MODE_MASTER)) {
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LOG_ERR("Slave mode is not supported");
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return -EIO;
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}
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/* This is deprecated and could be ignored in the future */
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if (dev_config & I2C_ADDR_10_BITS) {
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LOG_ERR("10-bit addressing mode is not supported");
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return -EIO;
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}
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/* Enables and configures I2C master */
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I2CMasterInitExpClk(get_dev_config(dev)->base,
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sys_clock_hw_cycles_per_sec(), fast);
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return 0;
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}
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static void i2c_cc13xx_cc26xx_isr(void *arg)
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{
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const u32_t base = get_dev_config(arg)->base;
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struct i2c_cc13xx_cc26xx_data *data = get_dev_data(arg);
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if (I2CMasterIntStatus(base, true)) {
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I2CMasterIntClear(base);
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data->error = I2CMasterErr(base);
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k_sem_give(&data->complete);
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}
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}
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static int i2c_cc13xx_cc26xx_init(struct device *dev)
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{
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u32_t cfg;
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int err;
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/* Enable I2C power domain */
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PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL);
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/* Enable I2C peripheral clock */
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PRCMPeripheralRunEnable(PRCM_PERIPH_I2C0);
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/* Enable in sleep mode until proper power managment is added */
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PRCMPeripheralSleepEnable(PRCM_PERIPH_I2C0);
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PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_I2C0);
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/* Load PRCM settings */
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PRCMLoadSet();
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while (!PRCMLoadGet()) {
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continue;
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}
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/* I2C should not be accessed until power domain is on. */
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while (PRCMPowerDomainStatus(PRCM_DOMAIN_SERIAL) !=
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PRCM_DOMAIN_POWER_ON) {
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continue;
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}
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IRQ_CONNECT(DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0,
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DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0_PRIORITY,
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i2c_cc13xx_cc26xx_isr, DEVICE_GET(i2c_cc13xx_cc26xx), 0);
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irq_enable(DT_TI_CC13XX_CC26XX_I2C_0_IRQ_0);
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/* Configure IOC module to route SDA and SCL signals */
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IOCPinTypeI2c(get_dev_config(dev)->base, get_dev_config(dev)->sda_pin,
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get_dev_config(dev)->scl_pin);
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cfg = i2c_map_dt_bitrate(DT_TI_CC13XX_CC26XX_I2C_0_CLOCK_FREQUENCY);
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err = i2c_cc13xx_cc26xx_configure(dev, cfg | I2C_MODE_MASTER);
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if (err) {
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LOG_ERR("Failed to configure");
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return err;
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}
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I2CMasterIntEnable(get_dev_config(dev)->base);
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return 0;
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}
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static const struct i2c_driver_api i2c_cc13xx_cc26xx_driver_api = {
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.configure = i2c_cc13xx_cc26xx_configure,
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.transfer = i2c_cc13xx_cc26xx_transfer
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};
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static const struct i2c_cc13xx_cc26xx_config i2c_cc13xx_cc26xx_config = {
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.base = DT_TI_CC13XX_CC26XX_I2C_0_BASE_ADDRESS,
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.sda_pin = DT_TI_CC13XX_CC26XX_I2C_0_SDA_PIN,
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.scl_pin = DT_TI_CC13XX_CC26XX_I2C_0_SCL_PIN
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};
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static struct i2c_cc13xx_cc26xx_data i2c_cc13xx_cc26xx_data = {
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.lock = Z_SEM_INITIALIZER(i2c_cc13xx_cc26xx_data.lock, 1, 1),
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.complete = Z_SEM_INITIALIZER(i2c_cc13xx_cc26xx_data.complete, 0, 1),
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.error = I2C_MASTER_ERR_NONE
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};
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DEVICE_AND_API_INIT(i2c_cc13xx_cc26xx, DT_TI_CC13XX_CC26XX_I2C_0_LABEL,
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i2c_cc13xx_cc26xx_init, &i2c_cc13xx_cc26xx_data,
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&i2c_cc13xx_cc26xx_config, POST_KERNEL,
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CONFIG_I2C_INIT_PRIORITY, &i2c_cc13xx_cc26xx_driver_api);
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@ -5,6 +5,7 @@
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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@ -75,6 +76,17 @@
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status = "disabled";
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label = "UART_1";
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};
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i2c0: i2c@40002000 {
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compatible = "ti,cc13xx-cc26xx-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40002000 0x1000>;
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interrupts = <1 0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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status = "disabled";
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label = "I2C_0";
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};
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};
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};
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46
dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
Normal file
46
dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
Normal file
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@ -0,0 +1,46 @@
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#
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# Copyright (c) 2019 Brett Witherspoon
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: TI CC13xx / CC26xx I2C
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version: 0.1
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description: >
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This is a representation of the TI CC13xx / CC26xx I2C node
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inherits:
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!include i2c.yaml
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "ti,cc13xx-cc26xx-i2c"
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reg:
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type: array
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category: required
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description: mmio register space
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generation: define
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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sda-pin:
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type: int
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category: required
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description: SDA pin
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generation: define
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scl-pin:
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type: int
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category: required
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description: SCL pin
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generation: define
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...
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@ -11,6 +11,8 @@ zephyr_library_sources(
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driverlib/setup.c
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driverlib/chipinfo.c
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driverlib/aux_sysif.c
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# Required for CPUdelay which is not in ROM
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driverlib/cpu.c
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# Required for default CCFG confguration
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startup_files/ccfg.c
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)
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@ -53,4 +53,11 @@ config UART_CC13XX_CC26XX
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endif # SERIAL
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if I2C
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config I2C_CC13XX_CC26XX
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default y
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endif # I2C
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endif # SOC_SERIES_CC13X2_CC26X2
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