patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 7 Packages Projects Releases Wiki Activity

driver: uart: ns16550: convert to DT_INST_*

Browse source 
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.

Signed-off-by: Timo Teräs <timo.teras@iki.fi>
This commit is contained in:
Timo Teräs 2020-03-09 16:37:20 +02:00 committed by Andrew Boie
parent e740818093
commit 6fd168e9a1
49 changed files with 94 additions and 505 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/x86/core/early_serial.c
View file

@ -10,7 +10,7 @@
/* Super-primitive 8250/16550 serial output-only driver, 115200 8n1 */
#define PORT ((io_port_t)DT_UART_NS16550_PORT_0_BASE_ADDR)
#define PORT ((io_port_t)DT_INST_0_NS16550_BASE_ADDRESS)
#define REG_IER 0x01 /* Interrupt enable reg. */
#define REG_LCR 0x03 /* Line control reg. */

4
boards/arc/em_starterkit/Kconfig.defconfig
View file

@ -52,10 +52,6 @@ config UART_NS16550
default y
depends on SERIAL
config UART_NS16550_PORT_1
default y
depends on UART_CONSOLE
if SPI
config SPI_DW

4
boards/arc/emsdp/Kconfig.defconfig
View file

@ -30,8 +30,4 @@ config UART_NS16550
default y
depends on SERIAL
config UART_NS16550_PORT_0
default y
depends on UART_CONSOLE
endif # BOARD_EMSDP

1
boards/arm/bcm958401m2/bcm958401m2_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_NS16550=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_NS16550_PORT_1=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_FLASH_SIZE=0
CONFIG_FLASH_BASE_ADDRESS=0x0

4
boards/arm/mec1501modular_assy6885/Kconfig.defconfig
View file

@ -6,10 +6,6 @@ if BOARD_MEC1501MODULAR_ASSY6885
config BOARD
default "mec1501modular_assy6885"
config UART_NS16550_PORT_1
default y if UART_CONSOLE
depends on UART_NS16550
if PINMUX_XEC
config PINMUX_XEC_GPIO000_036

2
boards/arm/mec1501modular_assy6885/pinmux.c
View file

@ -158,7 +158,7 @@ static int board_pinmux_init(struct device *dev)
pinmux_pin_set(portf, MCHP_GPIO_250, MCHP_GPIO_CTRL_MUX_F0);
/* See table 2-4 from the data sheet for pin multiplexing*/
#ifdef CONFIG_UART_NS16550_PORT_1
#ifdef DT_NS16550_400F2800_BASE_ADDRESS
/* Set muxing, for UART 1 TX/RX and power up */
mchp_pcr_periph_slp_ctrl(PCR_UART1, MCHP_PCR_SLEEP_DIS);

4
boards/arm/mec15xxevb_assy6853/Kconfig.defconfig
View file

@ -6,10 +6,6 @@ if BOARD_MEC15XXEVB_ASSY6853
config BOARD
default "mec15xxevb_assy6853"
config UART_NS16550_PORT_2
default y if UART_CONSOLE
depends on UART_NS16550
if PINMUX_XEC
config PINMUX_XEC_GPIO000_036

2
boards/arm/mec15xxevb_assy6853/pinmux.c
View file

@ -158,7 +158,7 @@ static int board_pinmux_init(struct device *dev)
pinmux_pin_set(portf, MCHP_GPIO_250, MCHP_GPIO_CTRL_MUX_F0);
/* See table 2-4 from the data sheet for pin multiplexing*/
#ifdef CONFIG_UART_NS16550_PORT_2
#ifdef DT_NS16550_400F2C00_BASE_ADDRESS
/* Set muxing, for UART 2 TX/RX and power up */
mchp_pcr_periph_slp_ctrl(PCR_UART2, MCHP_PCR_SLEEP_DIS);

4
boards/arm/mec2016evb_assy6797/Kconfig.defconfig
View file

@ -6,8 +6,4 @@ if BOARD_MEC2016EVB_ASSY6797
config BOARD
default "mec2016evb_assy6797"
config UART_NS16550_PORT_0
default y if UART_CONSOLE
depends on UART_NS16550
endif # BOARD_MEC2016EVB_ASSY6797

4
boards/arm/mec2016evb_assy6797/pinmux.c
View file

@ -15,7 +15,7 @@ static int board_pinmux_init(struct device *dev)
ARG_UNUSED(dev);
/* See table 2-4 from the Data sheet*/
#ifdef CONFIG_UART_NS16550_PORT_0
#ifdef DT_NS16550_400F2400_BASE_ADDRESS
/* Set muxing, for UART 0 and power up */
PCR_INST->CLK_REQ_2_b.UART_0_CLK_REQ = 1;
UART0_INST->CONFIG = 0;
@ -24,7 +24,7 @@ static int board_pinmux_init(struct device *dev)
GPIO_100_137_INST->GPIO_105_PIN_CONTROL_b.MUX_CONTROL = 1;
#endif
#ifdef CONFIG_UART_NS16550_PORT_1
#ifdef DT_NS16550_400F2800_BASE_ADDRESS
/* Set muxing, for UART 1 and power up */
PCR_INST->CLK_REQ_2_b.UART_1_CLK_REQ = 1;
UART1_INST->CONFIG = 0;

1
boards/nios2/qemu_nios2/qemu_nios2_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_ALTERA_JTAG=y
CONFIG_UART_NS16550=y
CONFIG_UART_NS16550_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_INCLUDE_RESET_VECTOR=n
CONFIG_EXTRA_EXCEPTION_INFO=y

16
boards/x86/gpmrb/Kconfig.defconfig
View file

@ -12,22 +12,6 @@ config BOARD
config BUILD_OUTPUT_STRIPPED
default y
if UART_NS16550
config UART_NS16550_PORT_0
default y
config UART_NS16550_PORT_1
default y
config UART_NS16550_PORT_2
default y
config UART_NS16550_PORT_3
default y
endif # UART_NS16550
if I2C
config I2C_0

10
boards/x86/up_squared/Kconfig.defconfig
View file

@ -8,16 +8,6 @@ config BOARD
config BUILD_OUTPUT_STRIPPED
default y
if UART_NS16550
config UART_NS16550_PORT_0
default y
config UART_NS16550_PORT_1
default y
endif # UART_NS16550
if I2C
config I2C_0

11
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
View file

@ -85,19 +85,12 @@ config USB_DEVICE_PRODUCT
endif # USB
if UART_NS16550
config UART_NS16550_PORT_0
default y
if UART_NS16550_PORT_0
if SERIAL
config UART_INTERRUPT_DRIVEN
default y
endif # UART_NS16550_PORT_0
endif # UART_NS16550
endif # SERIAL
if I2C

12
drivers/serial/CMakeLists.txt
View file

@ -36,13 +36,11 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c)
if(CONFIG_UART_NS16550)
zephyr_library_sources(uart_ns16550.c)
foreach(NUM RANGE 0 3)
if (CONFIG_UART_NS16550_PORT_${NUM})
configure_file(
uart_ns16550_port_x.h
${PROJECT_BINARY_DIR}/include/generated/uart_ns16550_port_${NUM}.h
@ONLY
)
endif()
configure_file(
uart_ns16550_port_x.h
${PROJECT_BINARY_DIR}/include/generated/uart_ns16550_port_${NUM}.h
@ONLY
)
endforeach(NUM)
endif()

24
drivers/serial/Kconfig.ns16550
View file

@ -40,27 +40,3 @@ config UART_NS16550_ACCESS_WORD_ONLY
In some case, e.g. ARC HS Development kit, the peripheral space of ns
16550 (DesignWare UART) only allows word access, byte access will raise
exception.
menuconfig UART_NS16550_PORT_0
bool "Enable NS16550 Port 0"
depends on UART_NS16550
help
This tells the driver to configure the UART port at boot.
menuconfig UART_NS16550_PORT_1
bool "Enable NS16550 Port 1"
depends on UART_NS16550
help
This tells the driver to configure the UART port at boot.
menuconfig UART_NS16550_PORT_2
bool "Enable NS16550 Port 2"
depends on UART_NS16550
help
This tells the driver to configure the UART port at boot.
menuconfig UART_NS16550_PORT_3
bool "Enable NS16550 Port 3"
depends on UART_NS16550
help
This tells the driver to configure the UART port at boot.

40
drivers/serial/uart_ns16550.c
View file

@ -40,24 +40,24 @@
* Ditto for DLF and PCI(e).
*/
#if defined(DT_UART_NS16550_PORT_0_PCP) || \
defined(DT_UART_NS16550_PORT_1_PCP) || \
defined(DT_UART_NS16550_PORT_2_PCP) || \
defined(DT_UART_NS16550_PORT_3_PCP)
#if defined(DT_INST_0_NS16550_PCP) || \
defined(DT_INST_1_NS16550_PCP) || \
defined(DT_INST_2_NS16550_PCP) || \
defined(DT_INST_3_NS16550_PCP)
#define UART_NS16550_PCP_ENABLED
#endif
#if defined(DT_UART_NS16550_PORT_0_DLF) || \
defined(DT_UART_NS16550_PORT_1_DLF) || \
defined(DT_UART_NS16550_PORT_2_DLF) || \
defined(DT_UART_NS16550_PORT_3_DLF)
#if defined(DT_INST_0_NS16550_DLF) || \
defined(DT_INST_1_NS16550_DLF) || \
defined(DT_INST_2_NS16550_DLF) || \
defined(DT_INST_3_NS16550_DLF)
#define UART_NS16550_DLF_ENABLED
#endif
#if DT_UART_NS16550_PORT_0_PCIE || \
DT_UART_NS16550_PORT_1_PCIE || \
DT_UART_NS16550_PORT_2_PCIE || \
DT_UART_NS16550_PORT_3_PCIE
#if DT_INST_0_NS16550_PCIE || \
DT_INST_1_NS16550_PCIE || \
DT_INST_2_NS16550_PCIE || \
DT_INST_3_NS16550_PCIE
BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
#define UART_NS16550_PCIE_ENABLED
#include <drivers/pcie/pcie.h>
@ -222,8 +222,8 @@ BUILD_ASSERT_MSG(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
#define IIRC(dev) (DEV_DATA(dev)->iir_cache)
#ifdef DT_NS16550_REG_SHIFT
#define UART_REG_ADDR_INTERVAL (1<<DT_NS16550_REG_SHIFT)
#ifdef DT_INST_0_NS16550_REG_SHIFT
#define UART_REG_ADDR_INTERVAL (1<<DT_INST_0_NS16550_REG_SHIFT)
#endif
#ifdef UART_NS16550_ACCESS_IOPORT
@ -319,6 +319,7 @@ static int uart_ns16550_configure(struct device *dev,
unsigned int old_level; /* old interrupt lock level */
u8_t mdc = 0U;
ARG_UNUSED(dev_data);
ARG_UNUSED(dev_cfg);
#ifdef UART_NS16550_PCIE_ENABLED
@ -843,18 +844,7 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
#endif
};
#ifdef CONFIG_UART_NS16550_PORT_0
#include <uart_ns16550_port_0.h>
#endif
#ifdef CONFIG_UART_NS16550_PORT_1
#include <uart_ns16550_port_1.h>
#endif
#ifdef CONFIG_UART_NS16550_PORT_2
#include <uart_ns16550_port_2.h>
#endif
#ifdef CONFIG_UART_NS16550_PORT_3
#include <uart_ns16550_port_3.h>
#endif

64
drivers/serial/uart_ns16550_port_x.h
View file

@ -7,57 +7,65 @@
* This file is a template for cmake and is not meant to be used directly!
*/
#ifdef DT_INST_@NUM@_NS16550
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void irq_config_func_@NUM@(struct device *port);
#endif
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_@NUM@ = {
.devconf.port = DT_UART_NS16550_PORT_@NUM@_BASE_ADDR,
.devconf.sys_clk_freq = DT_UART_NS16550_PORT_@NUM@_CLK_FREQ,
.devconf.port = DT_INST_@NUM@_NS16550_BASE_ADDRESS,
.devconf.sys_clk_freq = DT_INST_@NUM@_NS16550_CLOCK_FREQUENCY,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.devconf.irq_config_func = irq_config_func_@NUM@,
#endif
#ifdef DT_UART_NS16550_PORT_@NUM@_PCP
.pcp = DT_UART_NS16550_PORT_@NUM@_PCP,
#ifdef DT_INST_@NUM@_NS16550_PCP
.pcp = DT_INST_@NUM@_NS16550_PCP,
#endif
#if DT_UART_NS16550_PORT_@NUM@_PCIE
#if DT_INST_@NUM@_NS16550_PCIE
.pcie = true,
.pcie_bdf = DT_UART_NS16550_PORT_@NUM@_BASE_ADDR,
.pcie_id = DT_UART_NS16550_PORT_@NUM@_SIZE,
.pcie_bdf = DT_INST_@NUM@_NS16550_BASE_ADDRESS,
.pcie_id = DT_INST_@NUM@_NS16550_SIZE,
#endif
};
static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_@NUM@ = {
.uart_config.baudrate = DT_UART_NS16550_PORT_@NUM@_BAUD_RATE,
#ifdef DT_INST_@NUM@_NS16550_CURRENT_SPEED
.uart_config.baudrate = DT_INST_@NUM@_NS16550_CURRENT_SPEED,
#endif
.uart_config.parity = UART_CFG_PARITY_NONE,
.uart_config.stop_bits = UART_CFG_STOP_BITS_1,
.uart_config.data_bits = UART_CFG_DATA_BITS_8,
#if DT_UART_NS16550_PORT_@NUM@_HW_FLOW_CONTROL
#if DT_INST_@NUM@_NS16550_HW_FLOW_CONTROL
.uart_config.flow_ctrl = UART_CFG_FLOW_CTRL_RTS_CTS,
#else
.uart_config.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,
#endif
#ifdef DT_UART_NS16550_PORT_@NUM@_DLF
.dlf = DT_UART_NS16550_PORT_@NUM@_DLF,
#ifdef DT_INST_@NUM@_NS16550_DLF
.dlf = DT_INST_@NUM@_NS16550_DLF,
#endif
};
DEVICE_AND_API_INIT(uart_ns16550_@NUM@, DT_UART_NS16550_PORT_@NUM@_NAME,
DEVICE_AND_API_INIT(uart_ns16550_@NUM@, DT_INST_@NUM@_NS16550_LABEL,
&uart_ns16550_init,
&uart_ns16550_dev_data_@NUM@, &uart_ns16550_dev_cfg_@NUM@,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&uart_ns16550_driver_api);
#ifndef DT_INST_@NUM@_NS16550_IRQ_0_SENSE
#define DT_INST_@NUM@_NS16550_IRQ_0_SENSE 0
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void irq_config_func_@NUM@(struct device *dev)
{
ARG_UNUSED(dev);
#if DT_UART_NS16550_PORT_@NUM@_PCIE
#if DT_UART_NS16550_PORT_@NUM@_IRQ == PCIE_IRQ_DETECT
#if DT_INST_@NUM@_NS16550_PCIE
#if DT_INST_@NUM@_NS16550_IRQ_0 == PCIE_IRQ_DETECT
/* PCI(e) with auto IRQ detection */
@ -66,44 +74,46 @@ static void irq_config_func_@NUM@(struct device *dev)
unsigned int irq;
irq = pcie_wired_irq(DT_UART_NS16550_PORT_@NUM@_BASE_ADDR);
irq = pcie_wired_irq(DT_INST_@NUM@_NS16550_BASE_ADDRESS);
if (irq == PCIE_CONF_INTR_IRQ_NONE) {
return;
}
irq_connect_dynamic(irq,
DT_UART_NS16550_PORT_@NUM@_IRQ_PRI,
DT_INST_@NUM@_NS16550_IRQ_0_PRIORITY,
uart_ns16550_isr,
DEVICE_GET(uart_ns16550_@NUM@),
DT_UART_NS16550_PORT_@NUM@_IRQ_FLAGS);
DT_INST_@NUM@_NS16550_IRQ_0_SENSE);
pcie_irq_enable(DT_UART_NS16550_PORT_@NUM@_BASE_ADDR, irq);
pcie_irq_enable(DT_INST_@NUM@_NS16550_BASE_ADDRESS, irq);
#else
/* PCI(e) with fixed or MSI IRQ */
IRQ_CONNECT(DT_UART_NS16550_PORT_@NUM@_IRQ,
DT_UART_NS16550_PORT_@NUM@_IRQ_PRI,
IRQ_CONNECT(DT_INST_@NUM@_NS16550_IRQ_0,
DT_INST_@NUM@_NS16550_IRQ_0_PRIORITY,
uart_ns16550_isr, DEVICE_GET(uart_ns16550_@NUM@),
DT_UART_NS16550_PORT_@NUM@_IRQ_FLAGS);
DT_INST_@NUM@_NS16550_IRQ_0_SENSE);
pcie_irq_enable(DT_UART_NS16550_PORT_@NUM@_BASE_ADDR,
DT_UART_NS16550_PORT_@NUM@_IRQ);
pcie_irq_enable(DT_INST_@NUM@_NS16550_BASE_ADDRESS,
DT_INST_@NUM@_NS16550_IRQ_0);
#endif
#else
/* not PCI(e) */
IRQ_CONNECT(DT_UART_NS16550_PORT_@NUM@_IRQ,
DT_UART_NS16550_PORT_@NUM@_IRQ_PRI,
IRQ_CONNECT(DT_INST_@NUM@_NS16550_IRQ_0,
DT_INST_@NUM@_NS16550_IRQ_0_PRIORITY,
uart_ns16550_isr, DEVICE_GET(uart_ns16550_@NUM@),
DT_UART_NS16550_PORT_@NUM@_IRQ_FLAGS);
DT_INST_@NUM@_NS16550_IRQ_0_SENSE);
irq_enable(DT_UART_NS16550_PORT_@NUM@_IRQ);
irq_enable(DT_INST_@NUM@_NS16550_IRQ_0);
#endif
}
#endif
#endif

3
dts/arm/microchip/mec1501hsz.dtsi
View file

@ -56,6 +56,7 @@
compatible = "ns16550";
reg = <0x400f2400 0x400>;
interrupts = <40 0>;
clock-frequency = <1843200>;
current-speed = <38400>;
label = "UART_0";
reg-shift = <0>;
@ -65,6 +66,7 @@
compatible = "ns16550";
reg = <0x400f2800 0x400>;
interrupts = <41 0>;
clock-frequency = <1843200>;
current-speed = <38400>;
label = "UART_1";
reg-shift = <0>;
@ -74,6 +76,7 @@
compatible = "ns16550";
reg = <0x400f2c00 0x400>;
interrupts = <44 0>;
clock-frequency = <1843200>;
current-speed = <38400>;
label = "UART_2";
reg-shift = <0>;

2
dts/arm/microchip/mec1701qsz.dtsi
View file

@ -32,6 +32,7 @@
compatible = "ns16550";
reg = <0x400f2400 0x400>;
interrupts = <40 0>;
clock-frequency = <1843200>;
current-speed = <38400>;
label = "UART_0";
reg-shift = <0>;
@ -41,6 +42,7 @@
compatible = "ns16550";
reg = <0x400f2800 0x400>;
interrupts = <41 0>;
clock-frequency = <1843200>;
current-speed = <38400>;
label = "UART_1";
reg-shift = <0>;

2
dts/nios2/nios2-qemu.dtsi
View file

@ -42,6 +42,8 @@
ns16550_uart: uart@440000 {
compatible = "ns16550";
reg = <0x440000 0x400>;
/* interrupts = <1 0>; */
clock-frequency = <50000000>;
label = "UART_0";
status = "disabled";

2
dts/nios2/nios2f.dtsi
View file

@ -35,6 +35,8 @@
uart0: uart@f0008000 {
compatible = "ns16550";
reg = <0xf0008000 0x400>;
clock-frequency = <50000000>;
/* interrupts = <1 0>; */
label = "UART_0";
status = "disabled";

8
soc/arc/snps_arc_hsdk/Kconfig.defconfig
View file

@ -46,14 +46,8 @@ config UART_NS16550
default y
depends on SERIAL
if UART_CONSOLE
config UART_NS16550_PORT_0
default y
config UART_NS16550_ACCESS_WORD_ONLY
default y
endif # UART_CONSOLE
depends on UART_NS16550
endif # ARC_HSDK

10
soc/arc/snps_arc_hsdk/dts_fixup.h
View file

@ -6,16 +6,6 @@
/* SoC level DTS fixup file */
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0005000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0005000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0005000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0005000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0005000_LABEL
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0005000_IRQ_0_PRIORITY
/*
* GPIO configuration
*/

7
soc/arc/snps_arc_hsdk/soc.h
View file

@ -32,13 +32,6 @@
#include <sys/util.h>
#include <random/rand32.h>
/*
* UARTs: UART0 & UART1 & UART2
*/
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
/* PINMUX IO Hardware Functions */
#define HSDK_PINMUX_FUNS 8

4
soc/arc/snps_arc_iot/Kconfig.defconfig
View file

@ -38,8 +38,4 @@ config UART_NS16550
default y
depends on SERIAL
config UART_NS16550_PORT_0
default y
depends on UART_CONSOLE
endif # ARC_IOT

47
soc/arc/snps_arc_iot/dts_fixup.h
View file

@ -13,51 +13,4 @@
#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_20000000_BASE_ADDRESS
#define DT_ICCM_SIZE (DT_ARC_ICCM_20000000_SIZE >> 10)
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80014000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80014000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80014000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80014000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80014000_LABEL
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80014000_IRQ_0_PRIORITY
#ifdef DT_NS16550_80014000_DLF
#define DT_UART_NS16550_PORT_0_DLF DT_NS16550_80014000_DLF
#endif
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_80014100_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_80014100_IRQ_0
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_80014100_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_80014100_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_80014100_LABEL
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_80014100_IRQ_0_PRIORITY
#ifdef DT_NS16550_80014100_DLF
#define DT_UART_NS16550_PORT_1_DLF DT_NS16550_80014100_DLF
#endif
#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_80014200_BASE_ADDRESS
#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_80014200_IRQ_0
#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_80014200_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_80014200_CURRENT_SPEED
#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_80014200_LABEL
#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_80014200_IRQ_0_PRIORITY
#ifdef DT_NS16550_80014200_DLF
#define DT_UART_NS16550_PORT_2_DLF DT_NS16550_80014200_DLF
#endif
#define DT_UART_NS16550_PORT_3_BASE_ADDR DT_NS16550_80014300_BASE_ADDRESS
#define DT_UART_NS16550_PORT_3_IRQ DT_NS16550_80014300_IRQ_0
#define DT_UART_NS16550_PORT_3_CLK_FREQ DT_NS16550_80014300_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_3_BAUD_RATE DT_NS16550_80014300_CURRENT_SPEED
#define DT_UART_NS16550_PORT_3_NAME DT_NS16550_80014300_LABEL
#define DT_UART_NS16550_PORT_3_IRQ_PRI DT_NS16550_80014300_IRQ_0_PRIORITY
#ifdef DT_NS16550_80014300_DLF
#define DT_UART_NS16550_PORT_3_DLF DT_NS16550_80014300_DLF
#endif
/* End of SoC Level DTS fixup file */

7
soc/arc/snps_arc_iot/soc.h
View file

@ -39,13 +39,6 @@
#include <sys/util.h>
#include <random/rand32.h>
/*
* UARTs: UART0 & UART1 & UART2
*/
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */

10
soc/arc/snps_emsdp/dts_fixup.h
View file

@ -13,16 +13,6 @@
#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_60000000_BASE_ADDRESS
#define DT_ICCM_SIZE (DT_ARC_ICCM_60000000_SIZE >> 10)
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0004000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0004000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0004000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0004000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0004000_LABEL
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0004000_IRQ_0_PRIORITY
/*
* GPIO configuration
*/

8
soc/arc/snps_emsdp/soc.h
View file

@ -24,17 +24,9 @@
#ifndef _ASMLANGUAGE
#include <sys/util.h>
#include <random/rand32.h>
/*
* UARTs: UART0 & UART1 & UART2
*/
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */
#endif /* _SOC_H_ */

24
soc/arc/snps_emsk/dts_fixup.h
View file

@ -12,30 +12,6 @@
#define DT_DDR_BASE_ADDRESS DT_MMIO_SRAM_10000000_BASE_ADDRESS
#define DT_DDR_SIZE (DT_MMIO_SRAM_10000000_SIZE >> 10)
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0008000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0008000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0008000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0008000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0008000_LABEL
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0008000_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_F0009000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_F0009000_IRQ_0
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_F0009000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_F0009000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_F0009000_LABEL
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_F0009000_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_F000A000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_F000A000_IRQ_0
#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_F000A000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_F000A000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_F000A000_LABEL
#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_F000A000_IRQ_0_PRIORITY
/*
* GPIO configuration
*/

7
soc/arc/snps_emsk/soc.h
View file

@ -45,13 +45,6 @@
#define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8)
/*
* UARTs: UART0 & UART1 & UART2
*/
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
#ifndef CONFIG_HAS_DTS
/* I2C */
/* I2C_0 is on Pmod2 connector */

16
soc/arc/snps_emsk/soc_config.c
View file

@ -18,14 +18,14 @@ static int uart_ns16550_init(struct device *dev)
/* On ARC EM Starter kit board,
* send the UART the command to clear the interrupt
*/
#ifdef CONFIG_UART_NS16550_PORT_0
sys_write32(0, DT_UART_NS16550_PORT_0_BASE_ADDR+0x4);
sys_write32(0, DT_UART_NS16550_PORT_0_BASE_ADDR+0x10);
#endif /* CONFIG_UART_NS16550_PORT_0 */
#ifdef CONFIG_UART_NS16550_PORT_1
sys_write32(0, DT_UART_NS16550_PORT_1_BASE_ADDR+0x4);
sys_write32(0, DT_UART_NS16550_PORT_1_BASE_ADDR+0x10);
#endif /* CONFIG_UART_NS16550_PORT_1 */
#ifdef DT_INST_0_NS16650
sys_write32(0, DT_INST_0_NS16550_BASE_ADDRESS+0x4);
sys_write32(0, DT_INST_0_NS16550_BASE_ADDRESS+0x10);
#endif /* DT_INST_0_NS16650 */
#ifdef DT_INST_1_NS16650
sys_write32(0, DT_INST_1_NS16550_BASE_ADDRESS+0x4);
sys_write32(0, DT_INST_1_NS16550_BASE_ADDRESS+0x10);
#endif /* DT_INST_1_NS16650 */
return 0;
}

14
soc/arm/bcm_vk/valkyrie/dts_fixup.h
View file

@ -8,18 +8,4 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_40020000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_40020000_LABEL
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_40020000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_40020000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_40020000_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_40020000_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_48100000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_48100000_LABEL
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_48100000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_48100000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_48100000_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_48100000_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */

6
soc/arm/bcm_vk/valkyrie/soc.h
View file

@ -282,10 +282,4 @@ typedef enum IRQn {
#define __MPU_PRESENT 1
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
/* CRMU UART */
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0
/* CHIP COMMON UART 0 */
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0
#endif

30
soc/arm/microchip_mec/mec1501/dts_fixup.h
View file

@ -21,36 +21,6 @@
#define DT_NS16550_REG_SHIFT DT_NS16550_400F2C00_REG_SHIFT
#endif
#define DT_UART_NS16550_PORT_0_BASE_ADDR \
DT_NS16550_400F2400_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_CLK_FREQ 1843200
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_400F2400_LABEL
#define DT_UART_NS16550_PORT_0_BAUD_RATE \
DT_NS16550_400F2400_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_400F2400_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_400F2400_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Deault */
#define DT_UART_NS16550_PORT_1_BASE_ADDR \
DT_NS16550_400F2800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_CLK_FREQ 1843200
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_400F2800_LABEL
#define DT_UART_NS16550_PORT_1_BAUD_RATE \
DT_NS16550_400F2800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_400F2800_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_400F2800_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
#define DT_UART_NS16550_PORT_2_BASE_ADDR \
DT_NS16550_400F2C00_BASE_ADDRESS
#define DT_UART_NS16550_PORT_2_CLK_FREQ 1843200
#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_400F2C00_LABEL
#define DT_UART_NS16550_PORT_2_BAUD_RATE \
DT_NS16550_400F2C00_CURRENT_SPEED
#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_400F2C00_IRQ_0
#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_400F2C00_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
/* Pin multiplexing and GPIOs share the same registers in the HW */
#define DT_PINMUX_XEC_GPIO000_036_BASE_ADDR DT_GPIO_XEC_GPIO000_036_BASE_ADDR
#define DT_PINMUX_XEC_GPIO040_076_BASE_ADDR DT_GPIO_XEC_GPIO040_076_BASE_ADDR

22
soc/arm/microchip_mec/mec1701/dts_fixup.h
View file

@ -8,25 +8,3 @@
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#if defined(DT_NS16550_400F2400_REG_SHIFT)
#define DT_NS16550_REG_SHIFT DT_NS16550_400F2400_REG_SHIFT
#elif defined(DT_NS16550_400F2800_REG_SHIFT)
#define DT_NS16550_REG_SHIFT DT_NS16550_400F2800_REG_SHIFT
#endif
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_400F2400_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_CLK_FREQ 1843200
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_400F2400_LABEL
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_400F2400_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_400F2400_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_400F2400_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Deault */
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_400F2800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_CLK_FREQ 1843200
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_400F2800_LABEL
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_400F2800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_400F2800_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_400F2800_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */

4
soc/nios2/nios2-qemu/dts_fixup.h
View file

@ -1,9 +1,5 @@
/* SPDX-License-Identifier: Apache-2.0 */
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_440000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_440000_LABEL
#define _RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define _RAM_SIZE (CONFIG_SRAM_SIZE * 1024)

5
soc/nios2/nios2-qemu/soc.h
View file

@ -10,8 +10,7 @@
#include <system.h>
#define DT_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE
#define DT_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ
#define DT_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ
/* Move to DTS once interrupt controller is defined there */
#define DT_INST_0_NS16550_IRQ_0 A_16550_UART_0_IRQ
#endif

7
soc/nios2/nios2f-zephyr/Kconfig.defconfig
View file

@ -23,11 +23,4 @@ config ALTERA_AVALON_MSGDMA
def_bool y
depends on DMA_NIOS2_MSGDMA
if UART_NS16550
config UART_NS16550_PORT_0
default y
endif # UART_NS16550
endif # SOC_NIOS2F_ZEPHYR

4
soc/nios2/nios2f-zephyr/dts_fixup.h
View file

@ -1,9 +1,5 @@
/* SPDX-License-Identifier: Apache-2.0 */
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0008000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0008000_LABEL
#define _RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define _RAM_SIZE (CONFIG_SRAM_SIZE * 1024)

5
soc/nios2/nios2f-zephyr/soc.h
View file

@ -10,8 +10,7 @@
#include <system.h>
#define DT_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE
#define DT_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ
#define DT_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ
/* Move to DTS once interrupt controller is defined there */
#define DT_INST_0_NS16550_IRQ_0 A_16550_UART_0_IRQ
#endif

56
soc/x86/apollo_lake/dts_fixup.h
View file

@ -11,60 +11,4 @@
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_INST_0_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_INST_0_NS16550_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_INST_0_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_INST_0_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_INST_0_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_INST_0_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_PCIE DT_INST_0_NS16550_PCIE
#ifdef DT_NS16550_0_PCP
#define DT_UART_NS16550_PORT_0_PCP DT_NS16550_0_PCP
#endif
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_INST_1_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_SIZE DT_INST_1_NS16550_SIZE
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_INST_1_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_INST_1_NS16550_LABEL
#define DT_UART_NS16550_PORT_1_IRQ DT_INST_1_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_INST_1_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_INST_1_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_INST_1_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_PCIE DT_INST_1_NS16550_PCIE
#ifdef DT_NS16550_1_PCP
#define DT_UART_NS16550_PORT_1_PCP DT_NS16550_1_PCP
#endif
#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_INST_2_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_2_SIZE DT_INST_2_NS16550_SIZE
#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_INST_2_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_2_NAME DT_INST_2_NS16550_LABEL
#define DT_UART_NS16550_PORT_2_IRQ DT_INST_2_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_INST_2_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS DT_INST_2_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_INST_2_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_2_PCIE DT_INST_2_NS16550_PCIE
#ifdef DT_NS16550_2_PCP
#define DT_UART_NS16550_PORT_2_PCP DT_NS16550_2_PCP
#endif
#define DT_UART_NS16550_PORT_3_BASE_ADDR DT_INST_3_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_3_SIZE DT_INST_3_NS16550_SIZE
#define DT_UART_NS16550_PORT_3_BAUD_RATE DT_INST_3_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_3_NAME DT_INST_3_NS16550_LABEL
#define DT_UART_NS16550_PORT_3_IRQ DT_INST_3_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_3_IRQ_PRI DT_INST_3_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_3_IRQ_FLAGS DT_INST_3_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_3_CLK_FREQ DT_INST_3_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_3_PCIE DT_INST_3_NS16550_PCIE
#ifdef DT_NS16550_3_PCP
#define DT_UART_NS16550_PORT_3_PCP DT_NS16550_3_PCP
#endif
/* End of SoC Level DTS fixup file */

20
soc/x86/apollo_lake/soc.c
View file

@ -31,30 +31,26 @@ MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
#endif /* CONFIG_HPET_TIMER */
/* for UARTs */
#ifdef CONFIG_UART_NS16550
#ifdef CONFIG_UART_NS16550_PORT_0
MMU_BOOT_REGION(DT_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
#ifdef DT_INST_0_NS16550
MMU_BOOT_REGION(DT_INST_0_NS16550_BASE_ADDRESS, 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef CONFIG_UART_NS16550_PORT_1
MMU_BOOT_REGION(DT_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
#ifdef DT_INST_1_NS16550
MMU_BOOT_REGION(DT_INST_1_NS16550_BASE_ADDRESS, 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef CONFIG_UART_NS16550_PORT_2
MMU_BOOT_REGION(DT_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
#ifdef DT_INST_2_NS16550
MMU_BOOT_REGION(DT_INST_2_NS16550_BASE_ADDRESS, 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#ifdef CONFIG_UART_NS16550_PORT_3
MMU_BOOT_REGION(DT_UART_NS16550_PORT_3_BASE_ADDR, 0x1000,
#ifdef DT_INST_3_NS16550
MMU_BOOT_REGION(DT_INST_3_NS16550_BASE_ADDRESS, 0x1000,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif
#endif /* CONFIG_UART_NS16550 */
/* for I2C controllers */
#ifdef CONFIG_I2C

10
soc/x86/atom/Kconfig.defconfig
View file

@ -15,16 +15,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config CLFLUSH_DETECT
default y if CACHE_FLUSHING
if UART_NS16550
config UART_NS16550_PORT_0
default y
config UART_NS16550_PORT_1
default y
endif # UART_NS16550
if BT_UART
config UART_PIPE_ON_DEV_NAME

16
soc/x86/atom/dts_fixup.h
View file

@ -2,22 +2,6 @@
/* SoC level DTS fixup file */
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_3F8_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_3F8_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_3F8_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_2F8_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_2F8_LABEL
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_2F8_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS

10
soc/x86/ia32/Kconfig.defconfig
View file

@ -15,14 +15,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config CLFLUSH_DETECT
default y if CACHE_FLUSHING
if UART_NS16550
config UART_NS16550_PORT_0
default y
config UART_NS16550_PORT_1
default y
endif # UART_NS16550
endif

16
soc/x86/ia32/dts_fixup.h
View file

@ -2,22 +2,6 @@
/* SoC level DTS fixup file */
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_3F8_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_3F8_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_3F8_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_2F8_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_2F8_LABEL
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_2F8_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS

8
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -4,14 +4,6 @@
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80800_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80800_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024