soc: xtensa: imx8: Add pinctrl support

This commit introduces support for pinctrl-related operations
on i.MX8QM/QXP.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h>
+
+&iomuxc {
+	iomuxc_uart2_rx_uart0_rts_b: IOMUXC_UART2_RX_UART0_RTS_B {
+		pinmux = <SC_P_UART0_RTS_B IMX8QM_DMA_LPUART2_RX_UART0_RTS_B>;
+	};
+
+	iomuxc_uart2_tx_uart0_cts_b: IOMUXC_UART2_TX_UART0_CTS_B {
+		pinmux = <SC_P_UART0_CTS_B IMX8QM_DMA_LPUART2_TX_UART0_CTS_B>;
+	};
+};
+
+&pinctrl {
+	lpuart2_default: lpuart2_default {
+		group0 {
+			pinmux = <&iomuxc_uart2_rx_uart0_rts_b>,
+				<&iomuxc_uart2_tx_uart0_cts_b>;
+		};
+	};
+};

boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_imx8.dtsi>
+#include "nxp_adsp_imx8-pinctrl.dtsi"
 
 / {
 	model = "nxp_adsp_imx8";

boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h>
+
+&iomuxc {
+	iomuxc_uart2_rx_uart2_rx: IOMUXC_UART2_RX_UART2_RX {
+		pinmux = <SC_P_UART2_RX IMX8QXP_DMA_LPUART2_RX_UART2_RX>;
+	};
+
+	iomuxc_uart2_tx_uart2_tx: IOMUXC_UART2_TX_UART2_TX {
+		pinmux = <SC_P_UART2_TX IMX8QXP_DMA_LPUART2_TX_UART2_TX>;
+	};
+};
+
+&pinctrl {
+	lpuart2_default: lpuart2_default {
+		group0 {
+			pinmux = <&iomuxc_uart2_rx_uart2_rx>,
+				<&iomuxc_uart2_tx_uart2_tx>;
+		};
+	};
+};

boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_imx8.dtsi>
+#include "nxp_adsp_imx8x-pinctrl.dtsi"
 
 / {
 	model = "nxp_adsp_imx8x";

drivers/pinctrl/CMakeLists.txt

@@ -36,3 +36,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RA pinctrl_ra.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c)

drivers/pinctrl/Kconfig.imx

@@ -7,6 +7,13 @@ config PINCTRL_IMX
 	help
 	  Enable pin controller driver for NXP iMX series MCUs
 
+config PINCTRL_IMX_SCU
+	bool "Pin controller driver for SCU-based i.MX SoCs"
+	depends on DT_HAS_NXP_IMX_IOMUXC_SCU_ENABLED
+	default y
+	help
+	  Enable pin controller driver for SCU-based NXP i.MX SoCs.
+
 # TODO: Find better place for this option
 config MCUX_XBARA
 	bool "MCUX XBARA driver"

drivers/pinctrl/pinctrl_imx_scu.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/pinctrl.h>
+#include <svc/pad/pad_api.h>
+#include <main/ipc.h>
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins,
+			   uint8_t pin_cnt, uintptr_t reg)
+{
+	sc_ipc_t ipc_handle;
+	int ret, i;
+
+	ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
+	if (ret != SC_ERR_NONE) {
+		return -ENODEV;
+	}
+
+	for (i = 0; i < pin_cnt; i++) {
+		/* TODO: for now, pad configuration is not supported. As such,
+		 * the state of the pad is the following:
+		 *	1) Normal configuration (no OD)
+		 *	2) ISO off
+		 *	3) Pull select and drive strength initialized by another
+		 *	entity (e.g: SCFW, Linux etc...) or set to the default
+		 *	values as specified in the TRM.
+		 */
+		ret = sc_pad_set_mux(ipc_handle, pins[i].pad, pins[i].mux, 0, 0);
+		if (ret != SC_ERR_NONE) {
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}

dts/bindings/pinctrl/nxp,imx-iomuxc-scu.yaml

@@ -0,0 +1,25 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Use this compatible for i.MX boards on which the
+  IOMUXC is managed by the SCU.
+
+compatible: "nxp,imx-iomuxc-scu"
+
+include: base.yaml
+
+child-binding:
+  description: SCFW-based IOMUXC pin mux.
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        This is an array of values defining the pin mux selection
+        with the following format:
+
+          <pad, mux>
+
+        pad: Which pad to configure.
+        mux: Select which signal to route.

dts/bindings/pinctrl/nxp,imx8-pinctrl.yaml

@@ -0,0 +1,17 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Use this compatible for i.MX8QM/QXP boards.
+
+compatible: "nxp,imx8-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: i.MX8QM/QXP pin controller pin group
+  child-binding:
+    description: i.MX8QM/QXP pin controller pin configuration node.
+    properties:
+      pinmux:
+        required: true
+        type: phandles

dts/xtensa/nxp/nxp_imx8.dtsi

@@ -42,5 +42,12 @@
 			compatible = "nxp,imx-ccm";
 			#clock-cells = <3>;
 		};
+
+		iomuxc: iomuxc {
+			compatible = "nxp,imx-iomuxc-scu";
+			pinctrl: pinctrl {
+				compatible = "nxp,imx8-pinctrl";
+			};
+		};
 	};
 };

include/zephyr/dt-bindings/pinctrl/imx8qm-pinctrl.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
+
+/* values for pad field */
+#define SC_P_UART0_RTS_B 23
+#define SC_P_UART0_CTS_B 24
+
+/* mux values */
+#define IMX8QM_DMA_LPUART2_RX_UART0_RTS_B 2 /* UART0_RTS_B ---> DMA_LPUART2_RX */
+#define IMX8QM_DMA_LPUART2_TX_UART0_CTS_B 2 /* DMA_LPUART2_TX ---> UART0_CTS_B */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_ */

include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
+
+/* values for pad field */
+#define SC_P_UART2_TX 113
+#define SC_P_UART2_RX 114
+
+/* mux values */
+#define IMX8QXP_DMA_LPUART2_RX_UART2_RX 0 /* UART2_RX ---> DMA_LPUART2_RX */
+#define IMX8QXP_DMA_LPUART2_TX_UART2_TX 0 /* DMA_LPUART2_TX ---> UART2_TX */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ */

soc/xtensa/nxp_adsp/imx8/pinctrl_soc.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pinctrl_soc_pinmux {
+	uint32_t pad;
+	uint32_t mux;
+};
+
+typedef struct pinctrl_soc_pinmux pinctrl_soc_pin_t;
+
+#define IMX8_PINMUX(n)					\
+{							\
+	.pad = DT_PROP_BY_IDX(n, pinmux, 0),            \
+	.mux = DT_PROP_BY_IDX(n, pinmux, 1),            \
+},
+
+#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\
+	IMX8_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)		\
+	{ DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),     \
+				 DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_PINMUX) };
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ */