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dts: arm: ambiq: Update the GPIO instances

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Use the "ambiq,gpio" binding to combine the "ambiq,gpio-bank"
child nodes for Apollo4 Plus soc.
Also update the GPIO driver accordingly.

Signed-off-by: Aaron Ye <aye@ambiq.com>
This commit is contained in:
Aaron Ye 2023-12-01 20:05:52 +08:00 committed by Carles Cufí
parent a24f0f0b1d
commit 70ce5e4c6b
2 changed files with 65 additions and 42 deletions
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32
drivers/gpio/gpio_ambiq.c
View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
* Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_gpio
#define DT_DRV_COMPAT ambiq_gpio_bank
#include <errno.h>
#include <zephyr/drivers/gpio.h>
@ -20,7 +21,7 @@ typedef void (*ambiq_gpio_cfg_func_t)(void);
struct ambiq_gpio_config {
struct gpio_driver_config common;
uint32_t base;
uint32_t pin_offset;
uint32_t offset;
uint32_t irq_num;
ambiq_gpio_cfg_func_t cfg_func;
uint8_t ngpios;
@ -36,7 +37,7 @@ static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gp
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
pin += dev_cfg->pin_offset;
pin += (dev_cfg->offset >> 2);
am_hal_gpio_pincfg_t pincfg = am_hal_gpio_pincfg_default;
@ -81,7 +82,7 @@ static int ambiq_gpio_get_config(const struct device *dev, gpio_pin_t pin, gpio_
const struct ambiq_gpio_config *const dev_cfg = dev->config;
am_hal_gpio_pincfg_t pincfg;
pin += dev_cfg->pin_offset;
pin += (dev_cfg->offset >> 2);
am_hal_gpio_pinconfig_get(pin, &pincfg);
@ -126,11 +127,12 @@ static int ambiq_gpio_port_get_direction(const struct device *dev, gpio_port_pin
am_hal_gpio_pincfg_t pincfg;
gpio_port_pins_t ip = 0;
gpio_port_pins_t op = 0;
uint32_t pin_offset = dev_cfg->offset >> 2;
if (inputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + dev_cfg->pin_offset, &pincfg);
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.GP.cfg_b.eGPInput == AM_HAL_GPIO_PIN_INPUT_ENABLE) {
ip |= BIT(i);
}
@ -141,7 +143,7 @@ static int ambiq_gpio_port_get_direction(const struct device *dev, gpio_port_pin
if (outputs != NULL) {
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((map >> i) & 1) {
am_hal_gpio_pinconfig_get(i + dev_cfg->pin_offset, &pincfg);
am_hal_gpio_pinconfig_get(i + pin_offset, &pincfg);
if (pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL ||
pincfg.GP.cfg_b.eGPOutCfg == AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN) {
op |= BIT(i);
@ -159,7 +161,7 @@ static int ambiq_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
*value = (*AM_HAL_GPIO_RDn(dev_cfg->pin_offset));
*value = (*AM_HAL_GPIO_RDn(dev_cfg->offset >> 2));
return 0;
}
@ -168,10 +170,11 @@ static int ambiq_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pi
gpio_port_value_t value)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
uint32_t pin_offset = dev_cfg->offset >> 2;
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((mask >> i) & 1) {
am_hal_gpio_state_write(i + dev_cfg->pin_offset, ((value >> i) & 1));
am_hal_gpio_state_write(i + pin_offset, ((value >> i) & 1));
}
}
@ -181,10 +184,11 @@ static int ambiq_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pi
static int ambiq_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
uint32_t pin_offset = dev_cfg->offset >> 2;
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + dev_cfg->pin_offset, AM_HAL_GPIO_OUTPUT_SET);
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_SET);
}
}
@ -194,10 +198,11 @@ static int ambiq_gpio_port_set_bits_raw(const struct device *dev, gpio_port_pins
static int ambiq_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
uint32_t pin_offset = dev_cfg->offset >> 2;
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + dev_cfg->pin_offset, AM_HAL_GPIO_OUTPUT_CLEAR);
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_CLEAR);
}
}
@ -207,10 +212,11 @@ static int ambiq_gpio_port_clear_bits_raw(const struct device *dev, gpio_port_pi
static int ambiq_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
{
const struct ambiq_gpio_config *const dev_cfg = dev->config;
uint32_t pin_offset = dev_cfg->offset >> 2;
for (int i = 0; i < dev_cfg->ngpios; i++) {
if ((pins >> i) & 1) {
am_hal_gpio_state_write(i + dev_cfg->pin_offset, AM_HAL_GPIO_OUTPUT_TOGGLE);
am_hal_gpio_state_write(i + pin_offset, AM_HAL_GPIO_OUTPUT_TOGGLE);
}
}
@ -237,7 +243,7 @@ static int ambiq_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin
struct ambiq_gpio_data *const data = dev->data;
am_hal_gpio_pincfg_t pincfg;
int gpio_pin = pin + dev_cfg->pin_offset;
int gpio_pin = pin + (dev_cfg->offset >> 2);
uint32_t int_status;
int ret;
@ -334,7 +340,7 @@ static const struct gpio_driver_api ambiq_gpio_drv_api = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
}, \
.base = DT_REG_ADDR(DT_INST_PARENT(n)), \
.pin_offset = DT_INST_REG_ADDR(n), \
.offset = DT_INST_REG_ADDR(n), \
.ngpios = DT_INST_PROP(n, ngpios), \
.irq_num = DT_INST_IRQN(n), \
.cfg_func = ambiq_gpio_cfg_func_##n}; \

75
dts/arm/ambiq/ambiq_apollo4p.dtsi
View file

@ -210,40 +210,57 @@
#address-cells = <1>;
#size-cells = <0>;
gpio0_31: gpio0_31@0 {
gpio: gpio@40010000 {
compatible = "ambiq,gpio";
gpio-controller;
gpio-map-mask = <0xffffffe0 0xffffffc0>;
gpio-map-pass-thru = <0x1f 0x3f>;
gpio-map = <
0x00 0x0 &gpio0_31 0x0 0x0
0x20 0x0 &gpio32_63 0x0 0x0
0x40 0x0 &gpio64_95 0x0 0x0
0x60 0x0 &gpio96_127 0x0 0x0
>;
reg = <0x40010000>;
#gpio-cells = <2>;
reg = <0>;
interrupts = <56 0>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <0>;
ranges;
gpio32_63: gpio32_63@20 {
compatible = "ambiq,gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <32>;
interrupts = <57 0>;
status = "disabled";
};
gpio0_31: gpio0_31@0 {
compatible = "ambiq,gpio-bank";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
interrupts = <56 0>;
status = "disabled";
};
gpio64_95: gpio64_95@40 {
compatible = "ambiq,gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <64>;
interrupts = <58 0>;
status = "disabled";
};
gpio32_63: gpio32_63@80 {
compatible = "ambiq,gpio-bank";
gpio-controller;
#gpio-cells = <2>;
reg = <0x80>;
interrupts = <57 0>;
status = "disabled";
};
gpio96_127: gpio96_127@60 {
compatible = "ambiq,gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <96>;
interrupts = <59 0>;
status = "disabled";
gpio64_95: gpio64_95@100 {
compatible = "ambiq,gpio-bank";
gpio-controller;
#gpio-cells = <2>;
reg = <0x100>;
interrupts = <58 0>;
status = "disabled";
};
gpio96_127: gpio96_127@180 {
compatible = "ambiq,gpio-bank";
gpio-controller;
#gpio-cells = <2>;
reg = <0x180>;
interrupts = <59 0>;
status = "disabled";
};
};
};