drivers: spi_esp32_spim: Add support for IOMUX mode
In order to work on a clock speed higher than 20 MHz, IO MUX is required. Co-authored-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com> Signed-off-by: XiNGRZ Chan <hi@xingrz.me>
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@ -199,7 +199,7 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev,
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.clock_speed_hz = spi_cfg->frequency,
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.duty_cycle = cfg->duty_cycle == 0 ? 128 : cfg->duty_cycle,
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.input_delay_ns = cfg->input_delay_ns,
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.use_gpio = true
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.use_gpio = !cfg->use_iomux,
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};
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spi_hal_cal_clock_conf(&timing_param, &freq, &hal_dev->timing_conf);
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@ -365,6 +365,7 @@ static const struct spi_driver_api spi_api = {
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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.clock_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
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.use_iomux = DT_INST_PROP(idx, use_iomux), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, &spi_esp32_init, \
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@ -28,6 +28,7 @@ struct spi_esp32_config {
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int irq_source;
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const struct pinctrl_dev_config *pcfg;
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clock_control_subsys_t clock_subsys;
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bool use_iomux;
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};
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struct spi_esp32_data {
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@ -55,3 +55,14 @@ properties:
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type: boolean
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required: false
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description: Make CS positive during a transaction instead of negative
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use-iomux:
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type: boolean
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required: false
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description: |
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Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX
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routing mechanism instead, this avoids extra routing latency and makes
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possible the use of operating frequencies higher than 20 MHz.
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Refer to SoC's Technical Reference Manual to check which pins are
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allowed to use this routing path.
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