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arm64: update the value type of macro MPIDR_AFFLVL_MASK

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Fix build warning: left shift count >= width of type.
Such as in the case: mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This commit is contained in:
Hou Zhiqiang 2023-04-26 14:34:34 +08:00 committed by Anas Nashif
parent 92fcd9ef40
commit 71e86891c3
1 changed files with 1 additions and 1 deletions
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2
include/zephyr/arch/arm64/cpu.h
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@ -67,7 +67,7 @@
#define SCR_RES1 (BIT(4) | BIT(5))
/* MPIDR */
#define MPIDR_AFFLVL_MASK (0xff)
#define MPIDR_AFFLVL_MASK (0xffULL)
#define MPIDR_AFF0_SHIFT (0)
#define MPIDR_AFF1_SHIFT (8)