From 72312feeadcdffd6e0f5d5d0d73a75110c7109b7 Mon Sep 17 00:00:00 2001
From: Wilfried Chauveau <wilfried.chauveau@arm.com>
Date: Wed, 24 Jan 2024 12:02:13 +0000
Subject: [PATCH] arch: arm: cortex_m: Use cmsis api instead of inline asm in
 arch_irq_*

Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
---
 include/zephyr/arch/arm/asm_inline_gcc.h | 37 +++++++-----------------
 1 file changed, 11 insertions(+), 26 deletions(-)

diff --git a/include/zephyr/arch/arm/asm_inline_gcc.h b/include/zephyr/arch/arm/asm_inline_gcc.h
index 77729149e3..cb8653999f 100644
--- a/include/zephyr/arch/arm/asm_inline_gcc.h
+++ b/include/zephyr/arch/arm/asm_inline_gcc.h
@@ -21,6 +21,7 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/types.h>
 #include <zephyr/arch/arm/exception.h>
+#include <cmsis_core.h>
 
 #if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
 #include <zephyr/arch/arm/cortex_a_r/cpu.h>
@@ -46,25 +47,15 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 #if CONFIG_MP_MAX_NUM_CPUS == 1 || defined(CONFIG_ARMV8_M_BASELINE)
-	__asm__ volatile("mrs %0, PRIMASK;"
-		"cpsid i"
-		: "=r" (key)
-		:
-		: "memory");
+	key = __get_PRIMASK();
+	__disable_irq();
 #else
 #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
 #endif
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	unsigned int tmp;
-
-	__asm__ volatile(
-		"mov %1, %2;"
-		"mrs %0, BASEPRI;"
-		"msr BASEPRI_MAX, %1;"
-		"isb;"
-		: "=r"(key), "=r"(tmp)
-		: "i"(_EXC_IRQ_DEFAULT_PRIO)
-		: "memory");
+	key = __get_BASEPRI();
+	__set_BASEPRI_MAX(_EXC_IRQ_DEFAULT_PRIO);
+	__ISB();
 #elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	__asm__ volatile(
@@ -92,23 +83,17 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
 	if (key != 0U) {
 		return;
 	}
-	__asm__ volatile(
-		"cpsie i;"
-		"isb"
-		: : : "memory");
+	__enable_irq();
+	__ISB();
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile(
-		"msr BASEPRI, %0;"
-		"isb;"
-		:  : "r"(key) : "memory");
+	__set_BASEPRI(key);
+	__ISB();
 #elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	if (key != 0U) {
 		return;
 	}
-	__asm__ volatile(
-		"cpsie i;"
-		: : : "memory", "cc");
+	__enable_irq();
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */