drivers: clock_control: stm32h5: Set HSI divider

By default HSIDIV is set to 0x01, so default frequency is 32 MHz.
This register should be always set based on dts value.

Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
This commit is contained in:
Wojciech Slenska 2023-04-25 15:18:27 +02:00 committed by Carles Cufí
parent 0ebc37a972
commit 7271c3926f

View file

@ -20,6 +20,9 @@
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
/* Macros to fill up prescaler values */
#define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
#define hsi_divider(v) z_hsi_divider(v)
#define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define ahb_prescaler(v) z_ahb_prescaler(v)
@ -618,6 +621,8 @@ static void set_up_fixed_clock_sources(void)
/* Wait for HSI ready */
}
}
/* HSI divider configuration */
LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
}
if (IS_ENABLED(STM32_LSE_ENABLED)) {