gpio: Remove the k64 gpio driver

Now that we have a more generic mcux gpio driver that can be used across
multiple Kinetis SoCs, remove the specific k64 gpio driver.

Jira: ZEP-1394
Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2016-12-12 15:52:54 -06:00 committed by Kumar Gala
parent 4f5c2702da
commit 7682a0d7ca
6 changed files with 0 additions and 624 deletions

View file

@ -179,28 +179,6 @@ extern "C" {
#endif /* CONFIG_UART_K20 */
/*
* GPIO configuration settings
*/
#if defined(CONFIG_GPIO_K64)
#define GPIO_K64_A_BASE_ADDR 0x400FF000
#define GPIO_K64_A_IRQ IRQ_GPIO_PORTA
#define GPIO_K64_B_BASE_ADDR 0x400FF040
#define GPIO_K64_B_IRQ IRQ_GPIO_PORTB
#define GPIO_K64_C_BASE_ADDR 0x400FF080
#define GPIO_K64_C_IRQ IRQ_GPIO_PORTC
#define GPIO_K64_D_BASE_ADDR 0x400FF0C0
#define GPIO_K64_D_IRQ IRQ_GPIO_PORTD
#define GPIO_K64_E_BASE_ADDR 0x400FF100
#define GPIO_K64_E_IRQ IRQ_GPIO_PORTE
#endif /* CONFIG_GPIO_K64 */
#define PORT_K64_A_BASE_ADDR 0x40049000
#define PORT_K64_B_BASE_ADDR 0x4004A000
#define PORT_K64_C_BASE_ADDR 0x4004B000

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@ -53,8 +53,6 @@ source "drivers/gpio/Kconfig.qmsi"
source "drivers/gpio/Kconfig.sch"
source "drivers/gpio/Kconfig.k64"
source "drivers/gpio/Kconfig.mcux"
source "drivers/gpio/Kconfig.atmel_sam3"

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@ -1,133 +0,0 @@
# Kconfig.k64 - K64 GPIO configuration options
#
#
# Copyright (c) 2016 Intel Corporation
# Copyright (c) 2016 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
menuconfig GPIO_K64
bool "Freescale K64-based GPIO driver"
depends on GPIO && SOC_MK64F12
default n
help
Enable driver for Freescale K64-based GPIOs.
if GPIO_K64
config PORT_K64_INT_STATUS_OFFSET
hex "Freescale K64-based Port Control interrupt status register offset"
default 0xA0
config GPIO_K64_A
bool "Freescale K64-based GPIO Port A"
default n
help
Enable config options for Freescale K64-based GPIO port A.
config GPIO_K64_A_DEV_NAME
string "Freescale K64-based GPIO Port A Device Name"
depends on GPIO_K64_A
default "GPIO_0"
help
Specify the device name.
config GPIO_K64_PORTA_PRI
int "Freescale K64-based Port A interrupt priority"
depends on GPIO_K64_A
default 2
help
K64 Port A IRQ priority
config GPIO_K64_B
bool "Freescale K64-based GPIO Port B"
default n
help
Enable config options for Freescale K64-based GPIO port B.
config GPIO_K64_B_DEV_NAME
string "Freescale K64-based GPIO Port B Device Name"
depends on GPIO_K64_B
default "GPIO_1"
help
Specify the device name.
config GPIO_K64_PORTB_PRI
int "Freescale K64-based Port B interrupt priority"
depends on GPIO_K64_B
default 2
help
K64 Port B IRQ priority
config GPIO_K64_C
bool "Freescale K64-based GPIO Port B"
default n
help
Enable config options for Freescale K64-based GPIO port C.
config GPIO_K64_C_DEV_NAME
string "Freescale K64-based GPIO Port C Device Name"
depends on GPIO_K64_C
default "GPIO_2"
help
Specify the device name.
config GPIO_K64_PORTC_PRI
int "Freescale K64-based Port C interrupt priority"
depends on GPIO_K64_C
default 2
help
K64 Port C IRQ priority
config GPIO_K64_D
bool "Freescale K64-based GPIO Port D"
default n
help
Enable config options for Freescale K64-based GPIO port D.
config GPIO_K64_D_DEV_NAME
string "Freescale K64-based GPIO Port D Device Name"
depends on GPIO_K64_D
default "GPIO_3"
help
Specify the device name.
config GPIO_K64_PORTD_PRI
int "Freescale K64-based Port D interrupt priority"
depends on GPIO_K64_D
default 2
help
K64 Port D IRQ priority
config GPIO_K64_E
bool "Freescale K64-based GPIO Port E"
default n
help
Enable config options for Freescale K64-based GPIO port E.
config GPIO_K64_E_DEV_NAME
string "Freescale K64-based GPIO Port E Device Name"
depends on GPIO_K64_E
default "GPIO_4"
help
Specify the device name.
config GPIO_K64_PORTE_PRI
int "Freescale K64-based Port E interrupt priority"
depends on GPIO_K64_E
default 2
help
K64 Port E IRQ priority
endif # GPIO_K64

View file

@ -6,7 +6,6 @@ obj-$(CONFIG_GPIO_SCH) += gpio_sch.o
obj-$(CONFIG_GPIO_QMSI) += gpio_qmsi.o
obj-$(CONFIG_GPIO_QMSI_SS) += gpio_qmsi_ss.o
obj-$(CONFIG_GPIO_ATMEL_SAM3) += gpio_atmel_sam3.o
obj-$(CONFIG_GPIO_K64) += gpio_k64.o
obj-$(CONFIG_GPIO_MCUX) += gpio_mcux.o
obj-$(CONFIG_GPIO_STM32) += gpio_stm32.o
obj-$(CONFIG_GPIO_NRF5) += gpio_nrf5.o

View file

@ -1,415 +0,0 @@
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Driver for the Freescale K64 GPIO module.
*/
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <gpio.h>
#include <soc.h>
#include <sys_io.h>
#include <pinmux/k64/pinmux.h>
#include "gpio_k64.h"
#include "gpio_utils.h"
static int gpio_k64_config(struct device *dev,
int access_op, uint32_t pin, int flags)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
uint32_t value;
uint32_t setting;
uint8_t i;
/* check for an invalid pin configuration */
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
return -ENOTSUP;
}
/*
* Setup direction register:
* 0 - pin is input, 1 - pin is output
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
} else { /* GPIO_DIR_OUT */
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DIR_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
value = 0x0;
} else { /* GPIO_DIR_OUT */
value = 0xFFFFFFFF;
}
sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
}
/*
* Set up pullup/pulldown configuration, in Port Control module:
*/
if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_DN);
} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_NORMAL) {
setting = K64_PINMUX_PULL_DISABLE;
} else {
return -ENOTSUP;
}
/*
* Set up interrupt configuration, in Port Control module:
*/
if (flags & GPIO_INT) {
/* edge or level */
if (flags & GPIO_INT_EDGE) {
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_RISING;
} else if (flags & GPIO_INT_DOUBLE_EDGE) {
setting |= K64_PINMUX_INT_BOTH_EDGE;
} else {
setting |= K64_PINMUX_INT_FALLING;
}
} else { /* GPIO_INT_LEVEL */
if (flags & GPIO_INT_ACTIVE_HIGH) {
setting |= K64_PINMUX_INT_HIGH;
} else {
setting |= K64_PINMUX_INT_LOW;
}
}
}
/* write pull-up/-down and, if set, interrupt configuration settings */
if (access_op == GPIO_ACCESS_BY_PIN) {
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
/* clear, then set configuration values */
value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK;
}
/* Pins must configured as gpio */
value |= (setting | K64_PINMUX_FUNC_GPIO);
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(pin)));
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
/* clear, then set configuration values */
value = sys_read32((cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
value &= ~(K64_PINMUX_PULL_EN_MASK |
K64_PINMUX_PULL_SEL_MASK);
if (flags & GPIO_INT) {
value &= ~K64_PINMUX_INT_MASK;
}
/* Pins must configured as gpio */
value |= (setting | K64_PINMUX_FUNC_GPIO);
sys_write32(value, (cfg->port_base_addr +
K64_PINMUX_CTRL_OFFSET(i)));
}
}
return 0;
}
static int gpio_k64_write(struct device *dev,
int access_op, uint32_t pin, uint32_t value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
if (access_op == GPIO_ACCESS_BY_PIN) {
if (value) {
sys_set_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
} else {
sys_clear_bit((cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET), pin);
}
} else { /* GPIO_ACCESS_BY_PORT */
sys_write32(value, (cfg->gpio_base_addr +
GPIO_K64_DATA_OUT_OFFSET));
}
return 0;
}
static int gpio_k64_read(struct device *dev,
int access_op, uint32_t pin, uint32_t *value)
{
const struct gpio_k64_config * const cfg = dev->config->config_info;
*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
if (access_op == GPIO_ACCESS_BY_PIN) {
*value = (*value & BIT(pin)) >> pin;
}
/* nothing more to do for GPIO_ACCESS_BY_PORT */
return 0;
}
static int gpio_k64_manage_callback(struct device *dev,
struct gpio_callback *callback, bool set)
{
struct gpio_k64_data *data = dev->driver_data;
_gpio_manage_callback(&data->callbacks, callback, set);
return 0;
}
static int gpio_k64_enable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables |= BIT(pin);
} else {
data->pin_callback_enables = 0xFFFFFFFF;
}
return 0;
}
static int gpio_k64_disable_callback(struct device *dev,
int access_op, uint32_t pin)
{
struct gpio_k64_data *data = dev->driver_data;
if (access_op == GPIO_ACCESS_BY_PIN) {
data->pin_callback_enables &= ~BIT(pin);
} else {
data->pin_callback_enables = 0;
}
return 0;
}
/**
* @brief Handler for port interrupts
* @param dev Pointer to device structure for driver instance
*
* @return N/A
*/
static void gpio_k64_port_isr(void *dev)
{
struct device *port = (struct device *)dev;
struct gpio_k64_data *data = port->driver_data;
const struct gpio_k64_config *config = port->config->config_info;
mem_addr_t int_status_reg_addr;
uint32_t enabled_int, int_status;
int_status_reg_addr = config->port_base_addr +
CONFIG_PORT_K64_INT_STATUS_OFFSET;
int_status = sys_read32(int_status_reg_addr);
enabled_int = int_status & data->pin_callback_enables;
_gpio_fire_callbacks(&data->callbacks, port, enabled_int);
/* clear the port interrupts */
sys_write32(0xFFFFFFFF, int_status_reg_addr);
}
static const struct gpio_driver_api gpio_k64_drv_api_funcs = {
.config = gpio_k64_config,
.write = gpio_k64_write,
.read = gpio_k64_read,
.manage_callback = gpio_k64_manage_callback,
.enable_callback = gpio_k64_enable_callback,
.disable_callback = gpio_k64_disable_callback,
};
/* Initialization for Port A */
#ifdef CONFIG_GPIO_K64_A
static int gpio_k64_A_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_A_cfg = {
.gpio_base_addr = GPIO_K64_A_BASE_ADDR,
.port_base_addr = PORT_K64_A_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_A;
DEVICE_AND_API_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init,
&gpio_data_A, &gpio_k64_A_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_A_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_A_IRQ, CONFIG_GPIO_K64_PORTA_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0);
irq_enable(GPIO_K64_A_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_A */
/* Initialization for Port B */
#ifdef CONFIG_GPIO_K64_B
static int gpio_k64_B_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_B_cfg = {
.gpio_base_addr = GPIO_K64_B_BASE_ADDR,
.port_base_addr = PORT_K64_B_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_B;
DEVICE_AND_API_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init,
&gpio_data_B, &gpio_k64_B_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_B_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_B_IRQ, CONFIG_GPIO_K64_PORTB_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0);
irq_enable(GPIO_K64_B_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_B */
/* Initialization for Port C */
#ifdef CONFIG_GPIO_K64_C
static int gpio_k64_C_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_C_cfg = {
.gpio_base_addr = GPIO_K64_C_BASE_ADDR,
.port_base_addr = PORT_K64_C_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_C;
DEVICE_AND_API_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init,
&gpio_data_C, &gpio_k64_C_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_C_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_C_IRQ, CONFIG_GPIO_K64_PORTC_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0);
irq_enable(GPIO_K64_C_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_C */
/* Initialization for Port D */
#ifdef CONFIG_GPIO_K64_D
static int gpio_k64_D_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_D_cfg = {
.gpio_base_addr = GPIO_K64_D_BASE_ADDR,
.port_base_addr = PORT_K64_D_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_D;
DEVICE_AND_API_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init,
&gpio_data_D, &gpio_k64_D_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_D_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_D_IRQ, CONFIG_GPIO_K64_PORTD_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0);
irq_enable(GPIO_K64_D_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_D */
/* Initialization for Port E */
#ifdef CONFIG_GPIO_K64_E
static int gpio_k64_E_init(struct device *dev);
static const struct gpio_k64_config gpio_k64_E_cfg = {
.gpio_base_addr = GPIO_K64_E_BASE_ADDR,
.port_base_addr = PORT_K64_E_BASE_ADDR,
};
static struct gpio_k64_data gpio_data_E;
DEVICE_AND_API_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init,
&gpio_data_E, &gpio_k64_E_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
&gpio_k64_drv_api_funcs);
static int gpio_k64_E_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(GPIO_K64_E_IRQ, CONFIG_GPIO_K64_PORTE_PRI,
gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0);
irq_enable(GPIO_K64_E_IRQ);
return 0;
}
#endif /* CONFIG_GPIO_K64_E */

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@ -1,51 +0,0 @@
/*
* Copyright (c) 2016, Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Header file for the Freescale K64 GPIO module.
*/
#ifndef _GPIO_K64_H_
#define _GPIO_K64_H_
#include <kernel.h>
#include <gpio.h>
/* GPIO Port Register offsets */
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output */
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output */
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output */
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output */
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input */
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction */
/** Configuration data */
struct gpio_k64_config {
/* GPIO module base address */
uint32_t gpio_base_addr;
/* Port Control module base address */
uint32_t port_base_addr;
};
struct gpio_k64_data {
/* port ISR callback routine address */
sys_slist_t callbacks;
/* pin callback routine enable flags, by pin number */
uint32_t pin_callback_enables;
};
#endif /* _GPIO_K64_H_ */