gpio: Remove the k64 gpio driver
Now that we have a more generic mcux gpio driver that can be used across multiple Kinetis SoCs, remove the specific k64 gpio driver. Jira: ZEP-1394 Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
parent
4f5c2702da
commit
7682a0d7ca
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@ -179,28 +179,6 @@ extern "C" {
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#endif /* CONFIG_UART_K20 */
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/*
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* GPIO configuration settings
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*/
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#if defined(CONFIG_GPIO_K64)
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#define GPIO_K64_A_BASE_ADDR 0x400FF000
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#define GPIO_K64_A_IRQ IRQ_GPIO_PORTA
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#define GPIO_K64_B_BASE_ADDR 0x400FF040
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#define GPIO_K64_B_IRQ IRQ_GPIO_PORTB
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#define GPIO_K64_C_BASE_ADDR 0x400FF080
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#define GPIO_K64_C_IRQ IRQ_GPIO_PORTC
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#define GPIO_K64_D_BASE_ADDR 0x400FF0C0
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#define GPIO_K64_D_IRQ IRQ_GPIO_PORTD
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#define GPIO_K64_E_BASE_ADDR 0x400FF100
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#define GPIO_K64_E_IRQ IRQ_GPIO_PORTE
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#endif /* CONFIG_GPIO_K64 */
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#define PORT_K64_A_BASE_ADDR 0x40049000
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#define PORT_K64_B_BASE_ADDR 0x4004A000
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#define PORT_K64_C_BASE_ADDR 0x4004B000
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@ -53,8 +53,6 @@ source "drivers/gpio/Kconfig.qmsi"
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source "drivers/gpio/Kconfig.sch"
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source "drivers/gpio/Kconfig.k64"
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source "drivers/gpio/Kconfig.mcux"
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source "drivers/gpio/Kconfig.atmel_sam3"
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@ -1,133 +0,0 @@
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# Kconfig.k64 - K64 GPIO configuration options
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#
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#
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# Copyright (c) 2016 Intel Corporation
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# Copyright (c) 2016 Wind River Systems, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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menuconfig GPIO_K64
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bool "Freescale K64-based GPIO driver"
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depends on GPIO && SOC_MK64F12
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default n
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help
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Enable driver for Freescale K64-based GPIOs.
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if GPIO_K64
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config PORT_K64_INT_STATUS_OFFSET
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hex "Freescale K64-based Port Control interrupt status register offset"
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default 0xA0
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config GPIO_K64_A
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bool "Freescale K64-based GPIO Port A"
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default n
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help
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Enable config options for Freescale K64-based GPIO port A.
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config GPIO_K64_A_DEV_NAME
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string "Freescale K64-based GPIO Port A Device Name"
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depends on GPIO_K64_A
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default "GPIO_0"
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help
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Specify the device name.
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config GPIO_K64_PORTA_PRI
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int "Freescale K64-based Port A interrupt priority"
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depends on GPIO_K64_A
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default 2
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help
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K64 Port A IRQ priority
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config GPIO_K64_B
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bool "Freescale K64-based GPIO Port B"
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default n
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help
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Enable config options for Freescale K64-based GPIO port B.
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config GPIO_K64_B_DEV_NAME
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string "Freescale K64-based GPIO Port B Device Name"
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depends on GPIO_K64_B
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default "GPIO_1"
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help
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Specify the device name.
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config GPIO_K64_PORTB_PRI
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int "Freescale K64-based Port B interrupt priority"
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depends on GPIO_K64_B
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default 2
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help
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K64 Port B IRQ priority
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config GPIO_K64_C
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bool "Freescale K64-based GPIO Port B"
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default n
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help
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Enable config options for Freescale K64-based GPIO port C.
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config GPIO_K64_C_DEV_NAME
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string "Freescale K64-based GPIO Port C Device Name"
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depends on GPIO_K64_C
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default "GPIO_2"
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help
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Specify the device name.
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config GPIO_K64_PORTC_PRI
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int "Freescale K64-based Port C interrupt priority"
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depends on GPIO_K64_C
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default 2
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help
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K64 Port C IRQ priority
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config GPIO_K64_D
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bool "Freescale K64-based GPIO Port D"
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default n
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help
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Enable config options for Freescale K64-based GPIO port D.
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config GPIO_K64_D_DEV_NAME
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string "Freescale K64-based GPIO Port D Device Name"
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depends on GPIO_K64_D
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default "GPIO_3"
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help
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Specify the device name.
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config GPIO_K64_PORTD_PRI
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int "Freescale K64-based Port D interrupt priority"
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depends on GPIO_K64_D
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default 2
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help
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K64 Port D IRQ priority
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config GPIO_K64_E
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bool "Freescale K64-based GPIO Port E"
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default n
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help
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Enable config options for Freescale K64-based GPIO port E.
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config GPIO_K64_E_DEV_NAME
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string "Freescale K64-based GPIO Port E Device Name"
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depends on GPIO_K64_E
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default "GPIO_4"
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help
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Specify the device name.
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config GPIO_K64_PORTE_PRI
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int "Freescale K64-based Port E interrupt priority"
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depends on GPIO_K64_E
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default 2
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help
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K64 Port E IRQ priority
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endif # GPIO_K64
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@ -6,7 +6,6 @@ obj-$(CONFIG_GPIO_SCH) += gpio_sch.o
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obj-$(CONFIG_GPIO_QMSI) += gpio_qmsi.o
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obj-$(CONFIG_GPIO_QMSI_SS) += gpio_qmsi_ss.o
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obj-$(CONFIG_GPIO_ATMEL_SAM3) += gpio_atmel_sam3.o
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obj-$(CONFIG_GPIO_K64) += gpio_k64.o
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obj-$(CONFIG_GPIO_MCUX) += gpio_mcux.o
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obj-$(CONFIG_GPIO_STM32) += gpio_stm32.o
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obj-$(CONFIG_GPIO_NRF5) += gpio_nrf5.o
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@ -1,415 +0,0 @@
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/*
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* Copyright (c) 2016, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file Driver for the Freescale K64 GPIO module.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <gpio.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <pinmux/k64/pinmux.h>
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#include "gpio_k64.h"
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#include "gpio_utils.h"
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static int gpio_k64_config(struct device *dev,
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int access_op, uint32_t pin, int flags)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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uint32_t value;
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uint32_t setting;
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uint8_t i;
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/* check for an invalid pin configuration */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -ENOTSUP;
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}
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/*
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* Setup direction register:
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* 0 - pin is input, 1 - pin is output
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*/
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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sys_clear_bit((cfg->gpio_base_addr +
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GPIO_K64_DIR_OFFSET), pin);
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} else { /* GPIO_DIR_OUT */
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sys_set_bit((cfg->gpio_base_addr +
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GPIO_K64_DIR_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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value = 0x0;
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} else { /* GPIO_DIR_OUT */
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value = 0xFFFFFFFF;
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}
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sys_write32(value, (cfg->gpio_base_addr + GPIO_K64_DIR_OFFSET));
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}
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/*
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* Set up pullup/pulldown configuration, in Port Control module:
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*/
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_UP);
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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setting = (K64_PINMUX_PULL_ENABLE | K64_PINMUX_PULL_DN);
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_NORMAL) {
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setting = K64_PINMUX_PULL_DISABLE;
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} else {
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return -ENOTSUP;
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}
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/*
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* Set up interrupt configuration, in Port Control module:
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*/
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if (flags & GPIO_INT) {
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/* edge or level */
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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setting |= K64_PINMUX_INT_RISING;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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setting |= K64_PINMUX_INT_BOTH_EDGE;
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} else {
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setting |= K64_PINMUX_INT_FALLING;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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setting |= K64_PINMUX_INT_HIGH;
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} else {
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setting |= K64_PINMUX_INT_LOW;
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}
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}
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}
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/* write pull-up/-down and, if set, interrupt configuration settings */
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if (access_op == GPIO_ACCESS_BY_PIN) {
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value = sys_read32((cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(pin)));
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/* clear, then set configuration values */
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value &= ~(K64_PINMUX_PULL_EN_MASK | K64_PINMUX_PULL_SEL_MASK);
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if (flags & GPIO_INT) {
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value &= ~K64_PINMUX_INT_MASK;
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}
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/* Pins must configured as gpio */
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value |= (setting | K64_PINMUX_FUNC_GPIO);
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sys_write32(value, (cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(pin)));
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} else { /* GPIO_ACCESS_BY_PORT */
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for (i = 0; i < K64_PINMUX_NUM_PINS; i++) {
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/* clear, then set configuration values */
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value = sys_read32((cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(i)));
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value &= ~(K64_PINMUX_PULL_EN_MASK |
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K64_PINMUX_PULL_SEL_MASK);
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if (flags & GPIO_INT) {
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value &= ~K64_PINMUX_INT_MASK;
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}
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/* Pins must configured as gpio */
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value |= (setting | K64_PINMUX_FUNC_GPIO);
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sys_write32(value, (cfg->port_base_addr +
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K64_PINMUX_CTRL_OFFSET(i)));
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}
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}
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return 0;
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}
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static int gpio_k64_write(struct device *dev,
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int access_op, uint32_t pin, uint32_t value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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sys_set_bit((cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET), pin);
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} else {
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sys_clear_bit((cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET), pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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sys_write32(value, (cfg->gpio_base_addr +
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GPIO_K64_DATA_OUT_OFFSET));
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}
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return 0;
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}
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static int gpio_k64_read(struct device *dev,
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int access_op, uint32_t pin, uint32_t *value)
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{
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const struct gpio_k64_config * const cfg = dev->config->config_info;
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*value = sys_read32((cfg->gpio_base_addr + GPIO_K64_DATA_IN_OFFSET));
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (*value & BIT(pin)) >> pin;
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}
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/* nothing more to do for GPIO_ACCESS_BY_PORT */
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return 0;
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}
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static int gpio_k64_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_k64_data *data = dev->driver_data;
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_gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_k64_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_k64_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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} else {
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data->pin_callback_enables = 0xFFFFFFFF;
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}
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return 0;
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}
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static int gpio_k64_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_k64_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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data->pin_callback_enables = 0;
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}
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return 0;
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}
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/**
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* @brief Handler for port interrupts
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* @param dev Pointer to device structure for driver instance
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*
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* @return N/A
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*/
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static void gpio_k64_port_isr(void *dev)
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{
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struct device *port = (struct device *)dev;
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struct gpio_k64_data *data = port->driver_data;
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const struct gpio_k64_config *config = port->config->config_info;
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mem_addr_t int_status_reg_addr;
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uint32_t enabled_int, int_status;
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int_status_reg_addr = config->port_base_addr +
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CONFIG_PORT_K64_INT_STATUS_OFFSET;
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int_status = sys_read32(int_status_reg_addr);
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enabled_int = int_status & data->pin_callback_enables;
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_gpio_fire_callbacks(&data->callbacks, port, enabled_int);
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/* clear the port interrupts */
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sys_write32(0xFFFFFFFF, int_status_reg_addr);
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}
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static const struct gpio_driver_api gpio_k64_drv_api_funcs = {
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.config = gpio_k64_config,
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.write = gpio_k64_write,
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.read = gpio_k64_read,
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.manage_callback = gpio_k64_manage_callback,
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.enable_callback = gpio_k64_enable_callback,
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.disable_callback = gpio_k64_disable_callback,
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};
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/* Initialization for Port A */
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#ifdef CONFIG_GPIO_K64_A
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static int gpio_k64_A_init(struct device *dev);
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static const struct gpio_k64_config gpio_k64_A_cfg = {
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.gpio_base_addr = GPIO_K64_A_BASE_ADDR,
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.port_base_addr = PORT_K64_A_BASE_ADDR,
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};
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static struct gpio_k64_data gpio_data_A;
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DEVICE_AND_API_INIT(gpio_k64_A, CONFIG_GPIO_K64_A_DEV_NAME, gpio_k64_A_init,
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&gpio_data_A, &gpio_k64_A_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_k64_drv_api_funcs);
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static int gpio_k64_A_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(GPIO_K64_A_IRQ, CONFIG_GPIO_K64_PORTA_PRI,
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gpio_k64_port_isr, DEVICE_GET(gpio_k64_A), 0);
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irq_enable(GPIO_K64_A_IRQ);
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return 0;
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}
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#endif /* CONFIG_GPIO_K64_A */
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/* Initialization for Port B */
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#ifdef CONFIG_GPIO_K64_B
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static int gpio_k64_B_init(struct device *dev);
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|
||||
static const struct gpio_k64_config gpio_k64_B_cfg = {
|
||||
.gpio_base_addr = GPIO_K64_B_BASE_ADDR,
|
||||
.port_base_addr = PORT_K64_B_BASE_ADDR,
|
||||
};
|
||||
|
||||
static struct gpio_k64_data gpio_data_B;
|
||||
|
||||
DEVICE_AND_API_INIT(gpio_k64_B, CONFIG_GPIO_K64_B_DEV_NAME, gpio_k64_B_init,
|
||||
&gpio_data_B, &gpio_k64_B_cfg,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
||||
&gpio_k64_drv_api_funcs);
|
||||
|
||||
static int gpio_k64_B_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
IRQ_CONNECT(GPIO_K64_B_IRQ, CONFIG_GPIO_K64_PORTB_PRI,
|
||||
gpio_k64_port_isr, DEVICE_GET(gpio_k64_B), 0);
|
||||
|
||||
irq_enable(GPIO_K64_B_IRQ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_K64_B */
|
||||
|
||||
/* Initialization for Port C */
|
||||
#ifdef CONFIG_GPIO_K64_C
|
||||
|
||||
static int gpio_k64_C_init(struct device *dev);
|
||||
|
||||
static const struct gpio_k64_config gpio_k64_C_cfg = {
|
||||
.gpio_base_addr = GPIO_K64_C_BASE_ADDR,
|
||||
.port_base_addr = PORT_K64_C_BASE_ADDR,
|
||||
};
|
||||
|
||||
static struct gpio_k64_data gpio_data_C;
|
||||
|
||||
DEVICE_AND_API_INIT(gpio_k64_C, CONFIG_GPIO_K64_C_DEV_NAME, gpio_k64_C_init,
|
||||
&gpio_data_C, &gpio_k64_C_cfg,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
||||
&gpio_k64_drv_api_funcs);
|
||||
|
||||
static int gpio_k64_C_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
IRQ_CONNECT(GPIO_K64_C_IRQ, CONFIG_GPIO_K64_PORTC_PRI,
|
||||
gpio_k64_port_isr, DEVICE_GET(gpio_k64_C), 0);
|
||||
|
||||
irq_enable(GPIO_K64_C_IRQ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_K64_C */
|
||||
|
||||
/* Initialization for Port D */
|
||||
#ifdef CONFIG_GPIO_K64_D
|
||||
|
||||
static int gpio_k64_D_init(struct device *dev);
|
||||
|
||||
static const struct gpio_k64_config gpio_k64_D_cfg = {
|
||||
.gpio_base_addr = GPIO_K64_D_BASE_ADDR,
|
||||
.port_base_addr = PORT_K64_D_BASE_ADDR,
|
||||
};
|
||||
|
||||
static struct gpio_k64_data gpio_data_D;
|
||||
|
||||
DEVICE_AND_API_INIT(gpio_k64_D, CONFIG_GPIO_K64_D_DEV_NAME, gpio_k64_D_init,
|
||||
&gpio_data_D, &gpio_k64_D_cfg,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
||||
&gpio_k64_drv_api_funcs);
|
||||
|
||||
static int gpio_k64_D_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
IRQ_CONNECT(GPIO_K64_D_IRQ, CONFIG_GPIO_K64_PORTD_PRI,
|
||||
gpio_k64_port_isr, DEVICE_GET(gpio_k64_D), 0);
|
||||
|
||||
irq_enable(GPIO_K64_D_IRQ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_K64_D */
|
||||
|
||||
/* Initialization for Port E */
|
||||
#ifdef CONFIG_GPIO_K64_E
|
||||
|
||||
static int gpio_k64_E_init(struct device *dev);
|
||||
|
||||
static const struct gpio_k64_config gpio_k64_E_cfg = {
|
||||
.gpio_base_addr = GPIO_K64_E_BASE_ADDR,
|
||||
.port_base_addr = PORT_K64_E_BASE_ADDR,
|
||||
};
|
||||
|
||||
static struct gpio_k64_data gpio_data_E;
|
||||
|
||||
DEVICE_AND_API_INIT(gpio_k64_E, CONFIG_GPIO_K64_E_DEV_NAME, gpio_k64_E_init,
|
||||
&gpio_data_E, &gpio_k64_E_cfg,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
|
||||
&gpio_k64_drv_api_funcs);
|
||||
|
||||
static int gpio_k64_E_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
IRQ_CONNECT(GPIO_K64_E_IRQ, CONFIG_GPIO_K64_PORTE_PRI,
|
||||
gpio_k64_port_isr, DEVICE_GET(gpio_k64_E), 0);
|
||||
|
||||
irq_enable(GPIO_K64_E_IRQ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_K64_E */
|
|
@ -1,51 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Wind River Systems, Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file Header file for the Freescale K64 GPIO module.
|
||||
*/
|
||||
|
||||
#ifndef _GPIO_K64_H_
|
||||
#define _GPIO_K64_H_
|
||||
|
||||
#include <kernel.h>
|
||||
|
||||
#include <gpio.h>
|
||||
|
||||
/* GPIO Port Register offsets */
|
||||
#define GPIO_K64_DATA_OUT_OFFSET 0x00 /* Port Data Output */
|
||||
#define GPIO_K64_SET_OUT_OFFSET 0x04 /* Port Set Output */
|
||||
#define GPIO_K64_CLR_OUT_OFFSET 0x08 /* Port Clear Output */
|
||||
#define GPIO_K64_TOGGLE_OUT_OFFSET 0x0C /* Port Toggle Output */
|
||||
#define GPIO_K64_DATA_IN_OFFSET 0x10 /* Port Data Input */
|
||||
#define GPIO_K64_DIR_OFFSET 0x14 /* Port Data Direction */
|
||||
|
||||
|
||||
/** Configuration data */
|
||||
struct gpio_k64_config {
|
||||
/* GPIO module base address */
|
||||
uint32_t gpio_base_addr;
|
||||
/* Port Control module base address */
|
||||
uint32_t port_base_addr;
|
||||
};
|
||||
|
||||
struct gpio_k64_data {
|
||||
/* port ISR callback routine address */
|
||||
sys_slist_t callbacks;
|
||||
/* pin callback routine enable flags, by pin number */
|
||||
uint32_t pin_callback_enables;
|
||||
};
|
||||
#endif /* _GPIO_K64_H_ */
|
Loading…
Reference in a new issue