diff --git a/dts/arm64/broadcom/bcm2712.dtsi b/dts/arm64/broadcom/bcm2712.dtsi new file mode 100644 index 0000000000..b9985e23e7 --- /dev/null +++ b/dts/arm64/broadcom/bcm2712.dtsi @@ -0,0 +1,71 @@ +/* + * Copyright 2024 Myeonghyeon Park + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0>; + }; + }; + + interrupt-parent = <&gic>; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <1>; + + sram0: memory@200000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 0x200000 0x80000>; + }; + + gic: interrupt-controller@107fff9000 { + compatible = "arm,gic-v2", "arm,gic"; + reg = <0x10 0x7fff9000 0x1000>, + <0x10 0x7fffa000 0x2000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + gpio2@107d517c00 { + compatible = "simple-bus"; + reg = <0x10 0x7d517c00 0x40>; + + #address-cells = <1>; + #size-cells = <0>; + gio_aon: gpio@0 { + compatible = "brcm,brcmstb-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <17>; + status = "disabled"; + }; + }; + }; +}; diff --git a/soc/brcm/bcm2712/CMakeLists.txt b/soc/brcm/bcm2712/CMakeLists.txt new file mode 100644 index 0000000000..733abbebd9 --- /dev/null +++ b/soc/brcm/bcm2712/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/brcm/bcm2712/Kconfig b/soc/brcm/bcm2712/Kconfig new file mode 100644 index 0000000000..af683756c4 --- /dev/null +++ b/soc/brcm/bcm2712/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2024 Junho Lee +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2712 + select ARM64 + select CPU_CORTEX_A76 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/brcm/bcm2712/Kconfig.defconfig b/soc/brcm/bcm2712/Kconfig.defconfig new file mode 100644 index 0000000000..e408b20271 --- /dev/null +++ b/soc/brcm/bcm2712/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright 2024 Junho Lee +# SPDX-License-Identifier: Apache-2.0 + +if SOC_BCM2712 + +config NUM_IRQS + int + default 280 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 54000000 + +endif diff --git a/soc/brcm/bcm2712/Kconfig.soc b/soc/brcm/bcm2712/Kconfig.soc new file mode 100644 index 0000000000..3d55282e5d --- /dev/null +++ b/soc/brcm/bcm2712/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright 2024 Junho Lee +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2712 + bool + +config SOC + default "bcm2712" if SOC_BCM2712 diff --git a/soc/brcm/bcm2712/mmu_regions.c b/soc/brcm/bcm2712/mmu_regions.c new file mode 100644 index 0000000000..ea3314ffc2 --- /dev/null +++ b/soc/brcm/bcm2712/mmu_regions.c @@ -0,0 +1,26 @@ +/* + * Copyright 2024 Junho Lee + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("GIC", + DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1), + DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/brcm/bcm2712/soc.yml b/soc/brcm/bcm2712/soc.yml new file mode 100644 index 0000000000..ce95e07ac6 --- /dev/null +++ b/soc/brcm/bcm2712/soc.yml @@ -0,0 +1,4 @@ +series: +- name: bcm2712 + socs: + - name: bcm2712