arch: arm: cortex_m: move part of swap_helper to C
Asm is notoriously harder to maintain than C and requires core specific adaptation which impairs even more the readability of the code. This change significantly enhances the maintainability & portability of the code at the expanse of an indirection (1 outlined function). Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This commit is contained in:
Wilfried Chauveau
Carles Cufí
parent
d55ea8dba9
commit
773739a52a
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 Linaro, Limited
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* Copyright (c) 2023 Arm Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -47,3 +48,59 @@ int arch_swap(unsigned int key)
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*/
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return _current->arch.swap_return_value;
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}
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uintptr_t z_arm_pendsv_c(uintptr_t exc_ret)
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{
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/* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */
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IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
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(_kernel.cpus[0].current->arch.mode_exc_return = (uint8_t)exc_ret;));
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/* Protect the kernel state while we play with the thread lists */
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uint32_t basepri = arch_irq_lock();
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/* fetch the thread to run from the ready queue cache */
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struct k_thread *current = _kernel.cpus[0].current = _kernel.ready_q.cache;
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/*
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* Clear PendSV so that if another interrupt comes in and
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* decides, with the new kernel state based on the new thread
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* being context-switched in, that it needs to reschedule, it
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* will take, but that previously pended PendSVs do not take,
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* since they were based on the previous kernel state and this
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* has been handled.
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*/
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SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
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/* For Cortex-M, store TLS pointer in a global variable,
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* as it lacks the process ID or thread ID register
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* to be used by toolchain to access thread data.
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*/
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IF_ENABLED(CONFIG_THREAD_LOCAL_STORAGE,
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(extern uintptr_t z_arm_tls_ptr; z_arm_tls_ptr = current->tls));
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IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN,
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(exc_ret = (exc_ret & 0xFFFFFF00) | current->arch.mode_exc_return));
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/* Restore previous interrupt disable state (irq_lock key)
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* (We clear the arch.basepri field after restoring state)
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*/
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basepri = current->arch.basepri;
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current->arch.basepri = 0;
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arch_irq_unlock(basepri);
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#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
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/* Re-program dynamic memory map */
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z_arm_configure_dynamic_mpu_regions(current);
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#endif
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/* restore mode */
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IF_ENABLED(CONFIG_USERSPACE, ({
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CONTROL_Type ctrl = {.w = __get_CONTROL()};
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/* exit privileged state when returing to thread mode. */
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ctrl.b.nPRIV = 0;
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__set_CONTROL(ctrl.w | current->arch.mode);
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}));
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return exc_ret;
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}
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@ -27,6 +27,7 @@ _ASM_FILE_PROLOGUE
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GTEXT(z_arm_svc)
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GTEXT(z_arm_pendsv)
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GTEXT(z_do_kernel_oops)
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GTEXT(z_arm_pendsv_c)
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#if defined(CONFIG_USERSPACE)
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GTEXT(z_arm_do_syscall)
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#endif
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@ -117,125 +118,20 @@ out_fp_endif:
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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/* Protect the kernel state while we play with the thread lists */
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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cpsid i
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI_MAX, r0
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isb /* Make the effect of disabling interrupts be realized immediately */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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mov r4, lr
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mov r0, lr
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bl z_arm_pendsv_c
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mov lr, r4
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/*
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* Prepare to clear PendSV with interrupts unlocked, but
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* don't clear it yet. PendSV must not be cleared until
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* the new thread is context-switched in since all decisions
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* to pend PendSV have been taken with the current kernel
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* state and this is what we're handling currently.
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*/
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ldr r7, =_SCS_ICSR
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ldr r6, =_SCS_ICSR_UNPENDSV
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/* _kernel is still in r1 */
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/* fetch the thread to run from the ready queue cache */
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ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
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str r2, [r1, #_kernel_offset_to_current]
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/*
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* Clear PendSV so that if another interrupt comes in and
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* decides, with the new kernel state based on the new thread
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* being context-switched in, that it needs to reschedule, it
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* will take, but that previously pended PendSVs do not take,
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* since they were based on the previous kernel state and this
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* has been handled.
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*/
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/* _SCS_ICSR is still in r7 and _SCS_ICSR_UNPENDSV in r6 */
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str r6, [r7, #0]
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#if defined(CONFIG_THREAD_LOCAL_STORAGE)
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/* Grab the TLS pointer */
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ldr r4, =_thread_offset_to_tls
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adds r4, r2, r4
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ldr r0, [r4]
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/* For Cortex-M, store TLS pointer in a global variable,
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* as it lacks the process ID or thread ID register
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* to be used by toolchain to access thread data.
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*/
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ldr r4, =z_arm_tls_ptr
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str r0, [r4]
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#endif
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ldr r1, =_kernel
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ldr r2, [r1, #_kernel_offset_to_current]
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#if defined(CONFIG_ARM_STORE_EXC_RETURN)
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/* Restore EXC_RETURN value. */
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ldrsb lr, [r2, #_thread_offset_to_mode_exc_return]
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#endif
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/* Restore previous interrupt disable state (irq_lock key)
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* (We clear the arch.basepri field after restoring state)
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*/
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (_thread_offset_to_basepri > 124)
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/* Doing it this way since the offset to thread->arch.basepri can in
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* some configurations be larger than the maximum of 124 for ldr/str
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* immediate offsets.
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*/
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ldr r4, =_thread_offset_to_basepri
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adds r4, r2, r4
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ldr r0, [r4]
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movs.n r3, #0
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str r3, [r4]
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#else
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ldr r0, [r2, #_thread_offset_to_basepri]
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movs r3, #0
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str r3, [r2, #_thread_offset_to_basepri]
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mov lr, r0
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#endif
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* BASEPRI not available, previous interrupt disable state
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* maps to PRIMASK.
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*
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* Only enable interrupts if value is 0, meaning interrupts
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* were enabled before irq_lock was called.
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*/
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cmp r0, #0
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bne _thread_irq_disabled
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cpsie i
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_thread_irq_disabled:
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#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
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/* Re-program dynamic memory map */
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push {r2,lr}
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mov r0, r2
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bl z_arm_configure_dynamic_mpu_regions
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pop {r2,r3}
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mov lr, r3
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#endif
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#ifdef CONFIG_USERSPACE
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/* restore mode */
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ldr r3, =_thread_offset_to_mode
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adds r3, r2, r3
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ldr r0, [r3]
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mrs r3, CONTROL
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movs.n r1, #1
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bics r3, r1
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orrs r3, r0
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msr CONTROL, r3
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/* ISB is not strictly necessary here (stack pointer is not being
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* touched), but it's recommended to avoid executing pre-fetched
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* instructions with the previous privilege.
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*/
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isb
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#endif
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ldr r4, =_thread_offset_to_callee_saved
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adds r0, r2, r4
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@ -253,9 +149,6 @@ _thread_irq_disabled:
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subs r0, #36
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ldmia r0!, {r4-r7}
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* restore BASEPRI for the incoming thread */
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msr BASEPRI, r0
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#ifdef CONFIG_FPU_SHARING
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/* Assess whether switched-in thread had been using the FP registers. */
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tst lr, #_EXC_RETURN_FTYPE_Msk
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@ -285,30 +178,6 @@ in_fp_endif:
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isb
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#endif
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#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
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/* Re-program dynamic memory map */
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push {r2,lr}
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mov r0, r2 /* _current thread */
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bl z_arm_configure_dynamic_mpu_regions
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pop {r2,lr}
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#endif
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#ifdef CONFIG_USERSPACE
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/* restore mode */
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ldr r0, [r2, #_thread_offset_to_mode]
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mrs r3, CONTROL
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bic r3, #1
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orr r3, r0
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msr CONTROL, r3
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/* ISB is not strictly necessary here (stack pointer is not being
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* touched), but it's recommended to avoid executing pre-fetched
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* instructions with the previous privilege.
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*/
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isb
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#endif
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/* load callee-saved + psp from thread */
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add r0, r2, #_thread_offset_to_callee_saved
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ldmia r0, {r4-r11, ip}
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@ -429,7 +298,8 @@ _stack_frame_endif:
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#endif
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/* exception return is done in z_arm_int_exit() */
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b z_arm_int_exit
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ldr r0, =z_arm_int_exit
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bx r0
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#endif
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_oops:
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