nxp: hal: code update to reflect changes in SDK 2.13
HAL API changes in ethernet and pwm SoC RT595 power management code change west.yml update Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
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@ -113,6 +113,11 @@ enum eth_mcux_phy_state {
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eth_mcux_phy_state_closing
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};
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struct _phy_resource {
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mdioWrite write;
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mdioRead read;
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};
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#if defined(CONFIG_NET_POWER_MANAGEMENT)
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extern uint32_t ENET_GetInstance(ENET_Type * base);
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static const clock_ip_name_t enet_clocks[] = ENET_CLOCKS;
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@ -174,6 +179,7 @@ struct eth_context {
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#endif
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struct k_sem tx_buf_sem;
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phy_handle_t *phy_handle;
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struct _phy_resource *phy_config;
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struct k_sem rx_thread_sem;
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enum eth_mcux_phy_state phy_state;
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bool enabled;
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@ -446,7 +452,7 @@ static void eth_mcux_phy_event(struct eth_context *context)
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bool link_up;
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#if defined(CONFIG_SOC_SERIES_IMX_RT)
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status_t res;
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uint32_t ctrl2;
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uint16_t ctrl2;
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#endif
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phy_duplex_t phy_duplex = kPHY_FullDuplex;
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phy_speed_t phy_speed = kPHY_Speed100M;
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@ -625,7 +631,7 @@ static void eth_mcux_phy_setup(struct eth_context *context)
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{
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#if defined(CONFIG_SOC_SERIES_IMX_RT)
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status_t res;
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uint32_t oms_override;
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uint16_t oms_override;
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/* Disable MII interrupts to prevent triggering PHY events. */
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ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK);
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@ -1012,7 +1018,6 @@ static void eth_mcux_init(const struct device *dev)
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#endif
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context->phy_state = eth_mcux_phy_state_initial;
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context->phy_handle->mdioHandle->ops = &enet_ops;
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context->phy_handle->ops = &phyksz8081_ops;
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#if defined(CONFIG_SOC_SERIES_IMX_RT10XX)
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@ -1543,19 +1548,30 @@ static void eth_mcux_err_isr(const struct device *dev)
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tx_enet_frame_##n##_buf[NET_ETH_MAX_FRAME_SIZE]; \
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static _mcux_driver_buffer uint8_t \
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rx_enet_frame_##n##_buf[NET_ETH_MAX_FRAME_SIZE]; \
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static status_t _MDIO_Write(uint8_t phyAddr, uint8_t regAddr, uint16_t data) \
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{ \
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return ENET_MDIOWrite((ENET_Type *)DT_INST_REG_ADDR(n), phyAddr, regAddr, data);\
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}; \
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\
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static mdio_handle_t eth##n##_mdio_handle = { \
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.resource.base = (ENET_Type *)DT_INST_REG_ADDR(n), \
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}; \
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static status_t _MDIO_Read(uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) \
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{ \
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return ENET_MDIORead((ENET_Type *)DT_INST_REG_ADDR(n), phyAddr, regAddr, pData); \
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}; \
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\
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static struct _phy_resource eth##n##_phy_resource = { \
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.read = _MDIO_Read, \
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.write = _MDIO_Write \
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}; \
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static phy_handle_t eth##n##_phy_handle = { \
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.mdioHandle = ð##n##_mdio_handle, \
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}; \
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.resource = (void *)ð##n##_phy_resource \
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}; \
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static struct _phy_resource eth##n##_phy_config; \
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\
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static struct eth_context eth##n##_context = { \
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.base = (ENET_Type *)DT_INST_REG_ADDR(n), \
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.config_func = eth##n##_config_func, \
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.phy_addr = DT_INST_PROP(n, phy_addr), \
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.phy_config = ð##n##_phy_config, \
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.phy_addr = DT_INST_PROP(n, phy_addr), \
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.phy_duplex = kPHY_FullDuplex, \
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.phy_speed = kPHY_Speed100M, \
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.phy_handle = ð##n##_phy_handle, \
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@ -176,7 +176,11 @@ static int memc_flexspi_init(const struct device *dev)
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FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
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flexspi_config.enableCombination = data->combination_mode;
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#endif
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#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && \
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FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
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flexspi_config.enableSckBDiffOpt = data->sck_differential_clock;
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#endif
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flexspi_config.rxSampleClock = data->rx_sample_clock;
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/* Configure AHB RX buffers, if any configuration settings are present */
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@ -94,6 +94,7 @@ static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel,
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LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
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return -EINVAL;
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}
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data->channel[channel].pwmchannelenable = true;
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PWM_StopTimer(config->base, 1U << config->index);
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@ -152,7 +152,6 @@ static void usb_device_clock_init(void)
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/* Make sure USBHS ram buffer and usb1 phy has power up */
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POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM);
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POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM);
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POWER_DisablePD(kPDRUNCFG_LP_HSPAD_FSPI0_VDET);
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POWER_ApplyPD();
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RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn);
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