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tests: drivers: build_all: Build Altera FPGA driver

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Altera FPGA driver should be built on a regular basis to ensure
that there are no regressions

Signed-off-by: Hardeep Sharma <hardeep.sharma@intel.com>
This commit is contained in:
Hardeep Sharma 2024-04-23 10:56:32 +00:00 committed by Carles Cufí
parent b521bb655d
commit 792fd57d96
2 changed files with 17 additions and 0 deletions
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12
tests/drivers/build_all/fpga/app.overlay
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@ -38,6 +38,18 @@
#include "spi.dtsi" #include "spi.dtsi"
}; };
}; };
fpga0: bridges {
compatible = "altr,socfpga-agilex-bridge";
status = "okay";
};
sip_smc: smc {
compatible = "intel,socfpga-agilex-sip-smc";
method = "smc";
status = "okay";
zephyr,num-clients = <2>;
};
}; };
/* Put device specific modifications to properties or disabling of devices /* Put device specific modifications to properties or disabling of devices

5
tests/drivers/build_all/fpga/prj.conf
View file

@ -11,3 +11,8 @@ CONFIG_FPGA=y
# iCE40 FPGAs on a single bus to 1. # iCE40 FPGAs on a single bus to 1.
CONFIG_PINCTRL=n CONFIG_PINCTRL=n
CONFIG_ICE40_FPGA=y CONFIG_ICE40_FPGA=y
CONFIG_ALTERA_AGILEX_BRIDGE_FPGA=y
CONFIG_ARM_SIP_SVC_DRIVER=y
CONFIG_ARM_SIP_SVC_SUBSYS=y
CONFIG_ARM_SIP_SVC_SUBSYS_SINGLY_OPEN=y
CONFIG_HEAP_MEM_POOL_SIZE=16384