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arm: cortex-m: move synchronous SVC assessment in a separate function

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Move the assessment of a synchronous SVC error into a
separate function. This commit does not introduce any
behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2021-06-23 11:16:32 +02:00 committed by Christopher Friedt
parent a8d6c14d30
commit 7930829826
1 changed files with 20 additions and 11 deletions
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31
arch/arm/core/aarch32/cortex_m/fault.c
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@ -632,6 +632,25 @@ static void debug_monitor(z_arch_esf_t *esf, bool *recoverable)
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
static inline bool z_arm_is_synchronous_svc(z_arch_esf_t *esf)
{
uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
/* SVC is a 16-bit instruction. On a synchronous SVC
* escalated to Hard Fault, the return address is the
* next instruction, i.e. after the SVC.
*/
#define _SVC_OPCODE 0xDF00
uint16_t fault_insn = *(ret_addr - 1);
if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
return true;
}
#undef _SVC_OPCODE
return false;
}
/**
*
* @brief Dump hard fault information
@ -655,21 +674,11 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
* priority. We handle the case of Kernel OOPS and Stack
* Fail here.
*/
uint16_t *ret_addr = (uint16_t *)esf->basic.pc;
/* SVC is a 16-bit instruction. On a synchronous SVC
* escalated to Hard Fault, the return address is the
* next instruction, i.e. after the SVC.
*/
#define _SVC_OPCODE 0xDF00
uint16_t fault_insn = *(ret_addr - 1);
if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
if (z_arm_is_synchronous_svc(esf)) {
PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
reason = esf->basic.r0;
}
#undef _SVC_OPCODE
*recoverable = memory_fault_recoverable(esf, true);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)