boards: arm64: add support of Renesas Spider S4 A55 board

Add support of 'rcar_spider_s4/r8a779f0/a55' board: minimal dts
and configuration.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>

boards/renesas/rcar_spider_s4/Kconfig.defconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 EPAM Systems
+# SPDX-License-Identifier: Apache-2.0
+
+config BUILD_OUTPUT_BIN
+	default y if BOARD_RCAR_SPIDER_S4_R8A779F0_A55

boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4

@@ -2,4 +2,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_RCAR_SPIDER_S4
-	select SOC_R8A779F0
+	select SOC_R8A779F0_R52 if BOARD_RCAR_SPIDER_S4_R8A779F0_R52
+	select SOC_R8A779F0_A55 if BOARD_RCAR_SPIDER_S4_R8A779F0_A55

boards/renesas/rcar_spider_s4/board.cmake

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
-board_runner_args(openocd "--use-elf")
-include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+if(CONFIG_BOARD_RCAR_SPIDER_S4_R8A779F0_R52)
+  board_runner_args(openocd "--use-elf")
+  include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+endif()

boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst

@@ -0,0 +1,83 @@
+.. _rcar_spider_a55:
+
+R-CAR Spider S4 (ARM64)
+#######################
+
+Overview
+********
+R-Car S4 enables to launch Car Server/CoGW with high performance, high-speed networking,
+high security and high functional safety levels that are required as E/E architectures
+evolve into domains and zones. The R-Car S4 solution allows designers to re-use up to 88
+percent of software code developed for 3rd generation R-Car SoCs and RH850 MCU applications.
+The software package supports the real-time cores with various drivers and basic software
+such as Linux BSP and hypervisors.
+
+Hardware
+********
+The R-Car S4 includes:
+
+* eight 1.2GHz Arm Cortex-A55 cores, 2 cores x 4 clusters;
+* 1.0 GHz Arm Cortex-R52 core (hardware Lock step is supported);
+* two 400MHz G4MH cores (hardware Lock step is supported);
+* memory controller for LPDDR4X-3200 with 32bit bus (16bit x 1ch + 16bit x 1ch) with ECC;
+* SD card host interface / eMMC;
+* UFS 3.0 x 1 channel;
+* PCI Express Gen4.0 interface (Dual lane x 2ch);
+* ICUMX;
+* ICUMH;
+* SHIP-S x 3 channels;
+* AES Accerator x 8 channels;
+* CAN FD interface x 16 channels;
+* R-Switch2 (Ether);
+* 100base EtherAVB x 1 channel;
+* Gbit-EtherTSN x 3 channels;
+* 1 unit FlexRay (A,B 2ch) interface.
+
+Supported Features
+==================
+The Renesas ``rcar_spider_s4/r8a779f0/a55`` board configuration supports the following
+hardware features:
+
++-----------+------------------------------+--------------------------------+
+| Interface | Driver/components            | Support level                  |
++===========+==============================+================================+
+| PINCTRL   | pinctrl                      |                                |
++-----------+------------------------------+--------------------------------+
+| CLOCK     | clock_control                |                                |
++-----------+------------------------------+--------------------------------+
+| UART      | serial                       | interrupt-driven/polling       |
++-----------+------------------------------+--------------------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+Programming and Debugging
+*************************
+
+The onboard flash is not supported by Zephyr at this time. However, it is possible to
+load the Zephyr binary using U-Boot commands.
+
+One of the ways to load Zephyr is shown below.
+
+.. code-block:: console
+
+   tftp 0x48000000 <tftp_server_path/zephyr.bin>
+   booti 0x48000000
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rcar_spider_s4/r8a779f0/a55
+   :goals: build
+
+References
+**********
+
+- `Renesas R-Car Development Support website`_
+- `eLinux Spider page`_
+
+.. _Renesas R-Car Development Support website:
+   https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support
+
+.. _eLinux Spider page:
+   https://elinux.org/R-Car/Boards/Spider

boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst

@@ -141,12 +141,12 @@ Flashing
 
 First of all, open your serial terminal.
 
-Applications for the ``rcar_spider_s4`` board configuration can be built in the
+Applications for the ``rcar_spider_s4/r8a779f0/r52`` board configuration can be built in the
 usual way (see :ref:`build_an_application` for more details).
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: rcar_spider_s4
+   :board: rcar_spider_s4/r8a779f0/r52
    :goals: flash
 
 You should see the following message in the terminal:
@@ -165,7 +165,7 @@ Here is an example for the :ref:`hello_world` application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: rcar_spider_s4
+   :board: rcar_spider_s4/r8a779f0/r52
    :goals: debug
 
 You will then get access to a GDB session for debugging.

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f0.h>
+
+&pfc {
+	hscif0_data_tx_default: hscif0_data_tx_default {
+		pin = <PIN_HTX0 FUNC_HTX0>;
+	};
+
+	hscif0_data_rx_default: hscif0_data_rx_default {
+		pin = <PIN_HRX0 FUNC_HRX0>;
+	};
+};

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2023-2024 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+/dts-v1/;
+#include <mem.h>
+#include <arm64/renesas/r8a779f0.dtsi>
+#include "rcar_spider_s4_r8a779f0_a55-pinctrl.dtsi"
+
+/ {
+	model = "Renesas Spider CA55";
+	chosen {
+		zephyr,sram = &ram;
+		zephyr,console = &hscif0;
+		zephyr,shell-uart = &hscif0;
+	};
+
+	ram: memory@48000000 {
+		device_type = "mmio-sram";
+		reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>;
+	};
+};
+
+&hscif0 {
+	pinctrl-0 = <&hscif0_data_tx_default &hscif0_data_rx_default>;
+	pinctrl-names = "default";
+	current-speed = <1843200>;
+	status = "okay";
+};

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.yaml

@@ -0,0 +1,12 @@
+identifier: rcar_spider_s4/r8a779f0/a55
+name: Cortex A55 for Renesas Spider
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+supported:
+  - pinctrl
+  - gpio
+  - clock_control
+  - uart

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55_defconfig

@@ -0,0 +1,19 @@
+# Cache management
+CONFIG_CACHE_MANAGEMENT=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable clock control
+CONFIG_CLOCK_CONTROL=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=16666666
+
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_XIP=n
+CONFIG_MAX_XLAT_TABLES=24
+CONFIG_ARMV8_A_NS=y

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_r52.dts

@@ -7,12 +7,12 @@
 
 /dts-v1/;
 #include <arm/renesas/rcar/gen4/r8a779f0.dtsi>
-#include "rcar_spider_s4-pinctrl.dtsi"
+#include "rcar_spider_s4_r8a779f0_r52-pinctrl.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
 	model = "Renesas Spider board";
-	compatible = "renesas,spider-s4";
+	compatible = "renesas,spider-s4-cr52";
 
 	chosen {
 		zephyr,sram = &sram0;

boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_r52.yaml

@@ -1,4 +1,4 @@
-identifier: rcar_spider_s4
+identifier: rcar_spider_s4/r8a779f0/r52
 name: Cortex r52 for Renesas Spider
 type: mcu
 arch: arm

drivers/pinctrl/renesas/rcar/CMakeLists.txt

@@ -5,7 +5,8 @@ zephyr_library_sources(pfc_rcar.c)
 
 if (CONFIG_SOC_R8A77951_R7 OR CONFIG_SOC_R8A77951_A57)
   zephyr_library_sources(pfc_r8a77951.c)
+elseif (CONFIG_SOC_R8A779F0_R52 OR CONFIG_SOC_R8A779F0_A55)
+  zephyr_library_sources(pfc_r8a779f0.c)
 endif()
 
 zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c)
-zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c)

dts/arm64/renesas/r8a779f0.dtsi

@@ -0,0 +1,118 @@
+/*
+ * Device Tree Source for the R-Car S4 (R8A779F0) SoC
+ *
+ * Copyright (C) 2023 EPAM Systems.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <arm64/armv8-a.dtsi>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
+#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
+
+/ {
+	compatible = "renesas,r8a779f0";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a55: cpu@0 {
+			compatible = "arm,armv8";
+			reg = <0>;
+			device_type = "cpu";
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	};
+
+	reg_3p3v: regulator_3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_3p3v";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+	};
+
+	reg_1p8v: regulator_1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_1p8v";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		status = "okay";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@f1000000 {
+			compatible = "arm,gic-600", "arm,gic-v3", "arm,gic";
+			#interrupt-cells = <4>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0 0xf1000000 0 0x20000>,
+			      <0 0xf1060000 0 0x110000>;
+			status = "okay";
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a779f0-cpg-mssr";
+			reg = <0 0xe6150000 0 0x4000>;
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		mmc0: mmc@ee140000 {
+			compatible = "renesas,rcar-mmc";
+			reg = <0 0xee140000 0 0x2000>;
+			vmmc-supply = <&reg_3p3v>;
+			vqmmc-supply = <&reg_1p8v>;
+			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
+			max-bus-freq = <200000000>;
+			status = "disabled";
+		};
+
+		pfc: pin-controller@e6050000 {
+			compatible = "renesas,rcar-pfc";
+			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
+			      <0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>,
+			      <0 0xdfd91000 0 0x16c>, <0 0xdfd91800 0 0x16c>;
+		};
+
+		hscif0: serial@e6540000 {
+			compatible = "renesas,rcar-hscif";
+			reg = <0 0xe6540000 0 0x60>;
+			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>;
+			status = "disabled";
+		};
+	};
+};

soc/renesas/rcar/rcar_gen4/CMakeLists.txt

@@ -1,5 +1,11 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_include_directories(.)
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+if(CONFIG_SOC_R8A779F0_R52)
+  zephyr_include_directories(r52)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_R8A779F0_A55)
+  zephyr_include_directories(a55)
+  zephyr_library_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
+endif()

soc/renesas/rcar/rcar_gen4/Kconfig

@@ -1,10 +1,15 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_RCAR_GEN4
-	bool
+config SOC_R8A779F0_R52
 	select ARM
 	select CPU_CORTEX_R52
 	select GIC_SINGLE_SECURITY_STATE
 	select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
 	select ARM_ARCH_TIMER
+
+config SOC_R8A779F0_A55
+	select ARM64
+	select CPU_CORTEX_A55
+	select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
+	select ARM_ARCH_TIMER

soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0

@@ -1,7 +1,7 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_R8A779F0
+if SOC_SERIES_RCAR_GEN4
 
 config NUM_IRQS
 	default 1216 #960 SPI + 256 LPI
@@ -9,4 +9,4 @@ config NUM_IRQS
 config PINCTRL
 	default y
 
-endif # SOC_R8A779F0
+endif # SOC_SERIES_RCAR_GEN4

soc/renesas/rcar/rcar_gen4/Kconfig.soc

@@ -5,14 +5,20 @@ config SOC_SERIES_RCAR_GEN4
 	bool
 	select SOC_FAMILY_RENESAS_RCAR
 
-config SOC_R8A779F0
+config SOC_R8A779F0_R52
 	bool
 	select SOC_SERIES_RCAR_GEN4
 	help
-	  r8a779f0
+	  r8a779f0 r52
+
+config SOC_R8A779F0_A55
+	bool
+	select SOC_SERIES_RCAR_GEN4
+	help
+	  r8a779f0 a55
 
 config SOC_SERIES
 	default "rcar_gen4" if SOC_SERIES_RCAR_GEN4
 
 config SOC
-	default "r8a779f0" if SOC_R8A779F0
+	default "r8a779f0" if SOC_R8A779F0_R52 || SOC_R8A779F0_A55

soc/renesas/rcar/rcar_gen4/a55/mmu_regions.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE_nGnRnE | MT_RW | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE_nGnRnE | MT_RW | MT_NS),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/renesas/rcar/rcar_gen4/r52/pinctrl_soc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
+
+#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */

soc/renesas/rcar/soc.yml

@@ -11,3 +11,6 @@ family:
       - name: rcar_gen4
         socs:
           - name: r8a779f0
+            cpuclusters:
+              - name: r52
+              - name: a55