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tests: benchmarks: timing_info: Enable benchmarks for nios2.

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This patch provides support needed to get timing related
information from nios2 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This commit is contained in:
Adithya Baglody 2018-07-23 13:57:06 +05:30 committed by Anas Nashif
parent bb918d85f8
commit 79f65d4db7
6 changed files with 111 additions and 1 deletions
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18
arch/common/timing_info_bench.c
View file

@ -58,6 +58,24 @@ u64_t __common_var_swap_end_time;
#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#elif CONFIG_NIOS2
#include "altera_avalon_timer_regs.h"
#define TIMING_INFO_PRE_READ() \
(IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10))
#define TIMING_INFO_OS_GET_TIME() (SUBTRACT_CLOCK_CYCLES(\
((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE))))
#define TIMING_INFO_GET_TIMER_VALUE() (\
((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))
#define SUBTRACT_CLOCK_CYCLES(val) \
((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) \
<< 16 | \
(IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) \
- ((u32_t)val))
#else
/* Default case */
#error "Benchmarks have not been implemented for this architecture"

10
arch/nios2/core/irq_manage.c
View file

@ -72,6 +72,11 @@ void _enter_irq(u32_t ipending)
{
int index;
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_isr(void);
read_timer_start_of_isr();
#endif
_kernel.nested++;
#ifdef CONFIG_IRQ_OFFLOAD
@ -89,6 +94,11 @@ void _enter_irq(u32_t ipending)
ipending &= ~(1 << index);
ite = &_sw_isr_table[index];
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_isr(void);
read_timer_end_of_isr();
#endif
ite->isr(ite->arg);
}

54
arch/nios2/core/swap.S
View file

@ -22,6 +22,33 @@ GTEXT(_k_neg_eagain)
*/
SECTION_FUNC(exception.other, __swap)
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel)
/* Get the pointer to kernel->current */
ldw r11, _kernel_offset_to_current(r10)
stw r2, _thread_offset_to_r16(r11)
stw r3, _thread_offset_to_r17(r11)
stw r4, _thread_offset_to_r18(r11)
stw ra, _thread_offset_to_ra(r11)
stw sp, _thread_offset_to_sp(r11)
call read_timer_start_of_swap
/* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel)
/* Get the pointer to kernel->current */
ldw r11, _kernel_offset_to_current(r10)
ldw r2, _thread_offset_to_r16(r11)
ldw r3, _thread_offset_to_r17(r11)
ldw r4, _thread_offset_to_r18(r11)
ldw ra, _thread_offset_to_ra(r11)
ldw sp, _thread_offset_to_sp(r11)
#endif
/* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel)
@ -114,6 +141,33 @@ no_unlock:
#else
wrctl status, r3
#endif
#ifdef CONFIG_EXECUTION_BENCHMARKING
/* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel)
ldw r11, _kernel_offset_to_current(r10)
stw r2, _thread_offset_to_r16(r11)
stw r3, _thread_offset_to_r17(r11)
stw r4, _thread_offset_to_r18(r11)
stw ra, _thread_offset_to_ra(r11)
stw sp, _thread_offset_to_sp(r11)
call read_timer_end_of_swap
/* Get a reference to _kernel in r10 */
movhi r10, %hi(_kernel)
ori r10, r10, %lo(_kernel)
/* Get the pointer to kernel->current */
ldw r11, _kernel_offset_to_current(r10)
ldw r2, _thread_offset_to_r16(r11)
ldw r3, _thread_offset_to_r17(r11)
ldw r4, _thread_offset_to_r18(r11)
ldw ra, _thread_offset_to_ra(r11)
ldw sp, _thread_offset_to_sp(r11)
#endif
ret

10
drivers/timer/altera_avalon_timer_hal.c
View file

@ -19,12 +19,22 @@ static void timer_irq_handler(void *unused)
{
ARG_UNUSED(unused);
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_start_of_tick_handler(void);
read_timer_start_of_tick_handler();
#endif
accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
/* Clear the interrupt */
alt_handle_irq((void *)TIMER_0_BASE, TIMER_0_IRQ);
_sys_clock_tick_announce();
#ifdef CONFIG_EXECUTION_BENCHMARKING
extern void read_timer_end_of_tick_handler(void);
read_timer_end_of_tick_handler();
#endif
}
int _sys_clock_driver_init(struct device *device)

18
tests/benchmarks/timing_info/src/timing_info.h
View file

@ -68,6 +68,24 @@
#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
#elif CONFIG_NIOS2
#include "altera_avalon_timer_regs.h"
#define TIMING_INFO_PRE_READ() \
(IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10))
#define TIMING_INFO_OS_GET_TIME() (SUBTRACT_CLOCK_CYCLES(\
((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE))))
#define TIMING_INFO_GET_TIMER_VALUE() (\
((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))
#define SUBTRACT_CLOCK_CYCLES(val) \
((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) \
<< 16 | \
(IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) \
- ((u32_t)val))
#endif /* CONFIG_NRF_RTC_TIMER */
/******************************************************************************/

2
tests/benchmarks/timing_info/testcase.yaml
View file

@ -1,6 +1,6 @@
tests:
benchmark.timing.default_kernel:
arch_whitelist: x86 arm arc xtensa
arch_whitelist: x86 arm arc xtensa nios2
tags: benchmark
benchmark.timing.userspace:
filter: CONFIG_ARCH_HAS_USERSPACE