west.yml: update hal to v4.4.1 base
west.yml: update hal_espressif to use latest v4.4.1 updates. This change needs to be insync with esp32c3 timer changes, otherwise it breaks it. drivers: timer: update esp32c3 systimer to meet API changes. Systimer API was refactored in hal v4.4.1, which requires updates in esp32C3 systimer. Timer behavior is maintained as is. mcpwm: add v4.4.1 include reference, which was refactored as well. driver: spi: esp32: update internal structs to meet API changes. cmake: updated esp32 board to use HAL_ prefix as from west blobs requirement. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
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4928a69a06
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7a00f7b793
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@ -10,7 +10,7 @@ board_runner_args(openocd --gdb-init "flushregs")
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board_runner_args(openocd --gdb-init "mon reset halt")
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board_runner_args(openocd --gdb-init "thb main")
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set(ESP_IDF_PATH ${ZEPHYR_ESPRESSIF_MODULE_DIR})
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set(ESP_IDF_PATH ${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR})
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assert(ESP_IDF_PATH "ESP_IDF_PATH is not set")
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board_finalize_runner_args(esp32 "--esp-idf-path=${ESP_IDF_PATH}")
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@ -8,6 +8,7 @@
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#include <hal/mcpwm_hal.h>
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#include <hal/mcpwm_ll.h>
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#include "driver/mcpwm.h"
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#include <soc.h>
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#include <errno.h>
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@ -131,24 +131,24 @@ static int spi_esp32_init(const struct device *dev)
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return 0;
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}
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static inline spi_ll_io_mode_t spi_esp32_get_io_mode(uint16_t operation)
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static inline uint8_t spi_esp32_get_line_mode(uint16_t operation)
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{
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if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES)) {
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switch (operation & SPI_LINES_MASK) {
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case SPI_LINES_SINGLE:
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return SPI_LL_IO_MODE_NORMAL;
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return 1;
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case SPI_LINES_DUAL:
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return SPI_LL_IO_MODE_DUAL;
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return 2;
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case SPI_LINES_OCTAL:
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return SPI_LL_IO_MODE_QIO;
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return 8;
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case SPI_LINES_QUAD:
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return SPI_LL_IO_MODE_QUAD;
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return 4;
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default:
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break;
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}
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}
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return SPI_LL_IO_MODE_NORMAL;
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return 1;
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}
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static int IRAM_ATTR spi_esp32_configure(const struct device *dev,
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@ -206,6 +206,7 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev,
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.duty_cycle = cfg->duty_cycle == 0 ? 128 : cfg->duty_cycle,
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.input_delay_ns = cfg->input_delay_ns,
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.use_gpio = !cfg->use_iomux,
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};
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spi_hal_cal_clock_conf(&timing_param, &freq, &hal_dev->timing_conf);
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@ -215,7 +216,14 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev,
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hal_dev->tx_lsbfirst = spi_cfg->operation & SPI_TRANSFER_LSB ? 1 : 0;
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hal_dev->rx_lsbfirst = spi_cfg->operation & SPI_TRANSFER_LSB ? 1 : 0;
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data->trans_config.io_mode = spi_esp32_get_io_mode(spi_cfg->operation);
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data->trans_config.line_mode.data_lines = spi_esp32_get_line_mode(spi_cfg->operation);
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/* multiline for command and address not supported */
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data->trans_config.line_mode.addr_lines = 1;
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data->trans_config.line_mode.cmd_lines = 1;
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/* keep cs line after transmission not supported */
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data->trans_config.cs_keep_active = 0;
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/* SPI mode */
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hal_dev->mode = 0;
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@ -34,25 +34,30 @@ const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_NODELABEL(systimer0));
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static struct k_spinlock lock;
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static uint64_t last_count;
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/* Systimer HAL layer object */
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static systimer_hal_context_t systimer_hal;
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static void set_systimer_alarm(uint64_t time)
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{
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systimer_hal_select_alarm_mode(SYSTIMER_ALARM_0, SYSTIMER_ALARM_MODE_ONESHOT);
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systimer_hal_set_alarm_target(SYSTIMER_ALARM_0, time);
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systimer_hal_enable_alarm_int(SYSTIMER_ALARM_0);
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systimer_hal_select_alarm_mode(&systimer_hal,
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SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_ALARM_MODE_ONESHOT);
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systimer_hal_set_alarm_target(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0, time);
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systimer_hal_enable_alarm_int(&systimer_hal, SYSTIMER_LL_ALARM_OS_TICK_CORE0);
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}
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static uint64_t systimer_alarm(void)
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static uint64_t get_systimer_alarm(void)
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{
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return systimer_hal_get_time(SYSTIMER_COUNTER_1);
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return systimer_hal_get_time(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
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}
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static void sys_timer_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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systimer_ll_clear_alarm_int(SYSTIMER_ALARM_0);
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systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_LL_ALARM_OS_TICK_CORE0);
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t now = systimer_alarm();
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uint64_t now = get_systimer_alarm();
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uint32_t dticks = (uint32_t)((now - last_count) / CYC_PER_TICK);
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@ -80,7 +85,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
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ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint64_t now = systimer_alarm();
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uint64_t now = get_systimer_alarm();
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uint32_t adj, cyc = ticks * CYC_PER_TICK;
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/* Round up to next tick boundary. */
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@ -108,7 +113,7 @@ uint32_t sys_clock_elapsed(void)
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = ((uint32_t)systimer_alarm() - (uint32_t)last_count) / CYC_PER_TICK;
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uint32_t ret = ((uint32_t)get_systimer_alarm() - (uint32_t)last_count) / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return ret;
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@ -116,12 +121,12 @@ uint32_t sys_clock_elapsed(void)
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uint32_t sys_clock_cycle_get_32(void)
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{
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return (uint32_t)systimer_alarm();
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return (uint32_t)get_systimer_alarm();
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}
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uint64_t sys_clock_cycle_get_64(void)
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{
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return systimer_alarm();
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return get_systimer_alarm();
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}
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static int sys_clock_driver_init(const struct device *dev)
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@ -134,13 +139,14 @@ static int sys_clock_driver_init(const struct device *dev)
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NULL,
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NULL);
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systimer_hal_init();
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systimer_hal_connect_alarm_counter(SYSTIMER_ALARM_0, SYSTIMER_COUNTER_1);
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systimer_hal_enable_counter(SYSTIMER_COUNTER_1);
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systimer_hal_counter_can_stall_by_cpu(SYSTIMER_COUNTER_1, 0, true);
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last_count = systimer_alarm();
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set_systimer_alarm(last_count + CYC_PER_TICK);
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systimer_hal_init(&systimer_hal);
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systimer_hal_connect_alarm_counter(&systimer_hal,
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SYSTIMER_LL_ALARM_OS_TICK_CORE0, SYSTIMER_LL_COUNTER_OS_TICK);
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systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
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systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 0, true);
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last_count = get_systimer_alarm();
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set_systimer_alarm(last_count + CYC_PER_TICK);
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return 0;
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}
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