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drivers: watchdog: mcux_wdog32: add driver for the NXP Kinetis WDOG32

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Add driver shim for the NXP Kinetis WDOG32 module.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen 2019-05-20 23:13:52 +02:00 committed by Maureen Helm
parent fc23fd1989
commit 7cb92552f3
7 changed files with 283 additions and 2 deletions
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1
drivers/watchdog/CMakeLists.txt
View file

@ -8,3 +8,4 @@ zephyr_sources_ifdef(CONFIG_WDT_ESP32 wdt_esp32.c)
zephyr_sources_ifdef(CONFIG_WDT_SAM0 wdt_sam0.c)
zephyr_sources_ifdef(CONFIG_WDT_NRFX wdt_nrfx.c)
zephyr_sources_ifdef(CONFIG_WDT_MCUX_WDOG wdt_mcux_wdog.c)
zephyr_sources_ifdef(CONFIG_WDT_MCUX_WDOG32 wdt_mcux_wdog32.c)

2
drivers/watchdog/Kconfig
View file

@ -55,6 +55,6 @@ source "drivers/watchdog/Kconfig.sam0"
source "drivers/watchdog/Kconfig.nrfx"
source "drivers/watchdog/Kconfig.mcux_wdog"
source "drivers/watchdog/Kconfig.mcux"
endif

9
drivers/watchdog/Kconfig.mcux_wdog → drivers/watchdog/Kconfig.mcux
View file

@ -7,7 +7,14 @@
menuconfig WDT_MCUX_WDOG
bool "MCUX WDOG driver"
depends on HAS_MCUX && CLOCK_CONTROL
depends on HAS_MCUX && !HAS_MCUX_WDOG32 && CLOCK_CONTROL
select HAS_DTS_WDT
help
Enable the mcux wdog driver.
menuconfig WDT_MCUX_WDOG32
bool "MCUX WDOG32 driver"
depends on HAS_MCUX_WDOG32 && CLOCK_CONTROL
select HAS_DTS_WDT
help
Enable the mcux wdog32 driver.

222
drivers/watchdog/wdt_mcux_wdog32.c Normal file
View file

@ -0,0 +1,222 @@
/*
* Copyright (2) 2019 Vestas Wind Systems A/S
*
* Based on wdt_mcux_wdog.c, which is:
* Copyright (c) 2018, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <drivers/watchdog.h>
#include <drivers/clock_control.h>
#include <fsl_wdog32.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(wdt_mcux_wdog32);
#define MIN_TIMEOUT 1
struct mcux_wdog32_config {
WDOG_Type *base;
#ifdef DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY
u32_t clock_frequency;
#else /* !DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
char *clock_name;
clock_control_subsys_t clock_subsys;
#endif /* !DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
wdog32_clock_source_t clk_source;
wdog32_clock_prescaler_t clk_divider;
void (*irq_config_func)(struct device *dev);
};
struct mcux_wdog32_data {
wdt_callback_t callback;
wdog32_config_t wdog_config;
bool timeout_valid;
};
static int mcux_wdog32_setup(struct device *dev, u8_t options)
{
const struct mcux_wdog32_config *config = dev->config->config_info;
struct mcux_wdog32_data *data = dev->driver_data;
WDOG_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
data->wdog_config.workMode.enableStop =
(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
data->wdog_config.workMode.enableDebug =
(options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U;
WDOG32_Init(base, &data->wdog_config);
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_wdog32_disable(struct device *dev)
{
const struct mcux_wdog32_config *config = dev->config->config_info;
struct mcux_wdog32_data *data = dev->driver_data;
WDOG_Type *base = config->base;
WDOG32_Deinit(base);
data->timeout_valid = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
#define MSEC_TO_WDOG32_TICKS(clock_freq, divider, msec) \
((u32_t)(clock_freq * msec / 1000U / divider))
static int mcux_wdog32_install_timeout(struct device *dev,
const struct wdt_timeout_cfg *cfg)
{
const struct mcux_wdog32_config *config = dev->config->config_info;
struct mcux_wdog32_data *data = dev->driver_data;
u32_t clock_freq;
int div;
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
#ifdef DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY
clock_freq = config->clock_frequency;
#else /* !DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
struct device *clock_dev = device_get_binding(config->clock_name);
if (clock_dev == NULL) {
return -EINVAL;
}
if (clock_control_get_rate(clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
#endif /* !DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
div = config->clk_divider == kWDOG32_ClockPrescalerDivide1 ? 1U : 256U;
WDOG32_GetDefaultConfig(&data->wdog_config);
data->wdog_config.timeoutValue =
MSEC_TO_WDOG32_TICKS(clock_freq, div, cfg->window.max);
if (cfg->window.min) {
data->wdog_config.enableWindowMode = true;
data->wdog_config.windowValue =
MSEC_TO_WDOG32_TICKS(clock_freq, div, cfg->window.min);
} else {
data->wdog_config.enableWindowMode = false;
data->wdog_config.windowValue = 0;
}
if ((data->wdog_config.timeoutValue < MIN_TIMEOUT) ||
(data->wdog_config.timeoutValue < data->wdog_config.windowValue)) {
LOG_ERR("Invalid timeout");
return -EINVAL;
}
data->wdog_config.prescaler = config->clk_divider;
data->wdog_config.clockSource = config->clk_source;
data->wdog_config.enableInterrupt = cfg->callback != NULL;
data->callback = cfg->callback;
data->timeout_valid = true;
LOG_DBG("Installed timeout (timeoutValue = %d)",
data->wdog_config.timeoutValue);
return 0;
}
static int mcux_wdog32_feed(struct device *dev, int channel_id)
{
const struct mcux_wdog32_config *config = dev->config->config_info;
WDOG_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
WDOG32_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_wdog32_isr(void *arg)
{
struct device *dev = (struct device *)arg;
const struct mcux_wdog32_config *config = dev->config->config_info;
struct mcux_wdog32_data *data = dev->driver_data;
WDOG_Type *base = config->base;
u32_t flags;
flags = WDOG32_GetStatusFlags(base);
WDOG32_ClearStatusFlags(base, flags);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_wdog32_init(struct device *dev)
{
const struct mcux_wdog32_config *config = dev->config->config_info;
config->irq_config_func(dev);
return 0;
}
static const struct wdt_driver_api mcux_wdog32_api = {
.setup = mcux_wdog32_setup,
.disable = mcux_wdog32_disable,
.install_timeout = mcux_wdog32_install_timeout,
.feed = mcux_wdog32_feed,
};
#define TO_WDOG32_CLK_SRC(val) _DO_CONCAT(kWDOG32_ClockSource, val)
#define TO_WDOG32_CLK_DIV(val) _DO_CONCAT(kWDOG32_ClockPrescalerDivide, val)
static void mcux_wdog32_config_func_0(struct device *dev);
static const struct mcux_wdog32_config mcux_wdog32_config_0 = {
.base = (WDOG_Type *) DT_INST_0_NXP_KINETIS_WDOG32_BASE_ADDRESS,
#ifdef DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY
.clock_frequency = DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY,
#else /* !DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
.clock_name = DT_INST_0_NXP_KINETIS_WDOG32_CLOCK_CONTROLLER,
.clock_subsys = (clock_control_subsys_t)
DT_INST_0_NXP_KINETIS_WDOG32_CLOCK_NAME,
#endif /* DT_INST_0_NXP_KINETIS_WDOG32_CLOCKS_CLOCK_FREQUENCY */
.clk_source =
TO_WDOG32_CLK_SRC(DT_INST_0_NXP_KINETIS_WDOG32_CLK_SOURCE),
.clk_divider =
TO_WDOG32_CLK_DIV(DT_INST_0_NXP_KINETIS_WDOG32_CLK_DIVIDER),
.irq_config_func = mcux_wdog32_config_func_0,
};
static struct mcux_wdog32_data mcux_wdog32_data_0;
DEVICE_AND_API_INIT(mcux_wdog32_0, DT_INST_0_NXP_KINETIS_WDOG32_LABEL,
&mcux_wdog32_init, &mcux_wdog32_data_0,
&mcux_wdog32_config_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_wdog32_api);
static void mcux_wdog32_config_func_0(struct device *dev)
{
IRQ_CONNECT(DT_INST_0_NXP_KINETIS_WDOG32_IRQ_0,
DT_INST_0_NXP_KINETIS_WDOG32_IRQ_0_PRIORITY,
mcux_wdog32_isr, DEVICE_GET(mcux_wdog32_0), 0);
irq_enable(DT_INST_0_NXP_KINETIS_WDOG32_IRQ_0);
}

45
dts/bindings/watchdog/nxp,kinetis-wdog32.yaml Normal file
View file

@ -0,0 +1,45 @@
#
# Copyright (c) 2019 Vestas Wind Systems A/S
#
# SPDX-License-Identifier: Apache-2.0
#
title: NXP Kinetis watchdog (WDOG32) driver
version: 0.1
description: >
This is a representation of the Kinetis watchdog (WDOG32)
inherits:
!include base.yaml
properties:
compatible:
constraint: "nxp,kinetis-wdog32"
reg:
category: required
label:
category: required
interrupts:
category: required
clocks:
type: array
category: required
description: Clock gate control information
generation: structures
clk-source:
type: int
category: required
description: Watchdog counter clock source
generation: define
clk-divider:
type: int
description: Watchdog counter clock divider
generation: define
category: required

5
ext/hal/nxp/mcux/Kconfig
View file

@ -129,4 +129,9 @@ config HAS_MCUX_USB_EHCI
help
Set if the USB controller EHCI module is present in the SoC.
config HAS_MCUX_WDOG32
bool
help
Set if the watchdog (WDOG32) module is present in the SoC.
endif # HAS_MCUX

1
ext/hal/nxp/mcux/drivers/kinetis/CMakeLists.txt
View file

@ -28,6 +28,7 @@ zephyr_sources_ifdef(CONFIG_UART_MCUX_LPUART fsl_lpuart.c)
zephyr_sources_ifdef(CONFIG_COUNTER_MCUX_RTC fsl_rtc.c)
zephyr_sources_ifdef(CONFIG_RTC_MCUX fsl_rtc.c)
zephyr_sources_ifdef(CONFIG_WDT_MCUX_WDOG fsl_wdog.c)
zephyr_sources_ifdef(CONFIG_WDT_MCUX_WDOG32 fsl_wdog32.c)
zephyr_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN fsl_flexcan.c)
if(NOT CONFIG_ASSERT OR CONFIG_FORCE_NO_ASSERT)
zephyr_compile_definitions(NDEBUG) # squelch fsl_flexcan.c warning