soc: riscv: virt: reorganize SoC folder

Move out of riscv-privileged, and convert to single SoC (no
family/series).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

boards/riscv/qemu_riscv32/qemu_riscv32_defconfig

@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_RISCV_VIRT=y
 CONFIG_SOC_RISCV_VIRT=y
 CONFIG_BOARD_QEMU_RISCV32=y
 CONFIG_CONSOLE=y

boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig

@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_RISCV_VIRT=y
 CONFIG_SOC_RISCV_VIRT=y
 CONFIG_BOARD_QEMU_RISCV32_SMP=y
 CONFIG_CONSOLE=y

boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig

@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_RISCV_VIRT=y
 CONFIG_SOC_RISCV_VIRT=y
 CONFIG_BOARD_QEMU_RISCV32E=y
 CONFIG_CONSOLE=y

boards/riscv/qemu_riscv64/qemu_riscv64_defconfig

@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_RISCV_VIRT=y
 CONFIG_SOC_RISCV_VIRT=y
 CONFIG_BOARD_QEMU_RISCV64=y
 CONFIG_PRIVILEGED_STACK_SIZE=2048

boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig

@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_RISCV_VIRT=y
 CONFIG_SOC_RISCV_VIRT=y
 CONFIG_BOARD_QEMU_RISCV64_SMP=y
 CONFIG_PRIVILEGED_STACK_SIZE=2048

soc/riscv/riscv-privileged/virt/Kconfig.series

@@ -1,7 +0,0 @@
-# Copyright (c) 2020 Cobham Gaisler AB
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_RISCV_VIRT
-	bool "QEMU RISC-V VirtIO Board"
-	select RISCV
-	select RISCV_PRIVILEGED

soc/riscv/virt/Kconfig.defconfig

@@ -1,9 +1,9 @@
 # Copyright (c) 2020 Cobham Gaisler AB
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_RISCV_VIRT
+if SOC_RISCV_VIRT
 
-config SOC_SERIES
+config SOC
 	default "virt"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC

soc/riscv/virt/Kconfig.soc

@@ -1,10 +1,6 @@
 # Copyright (c) 2020 Cobham Gaisler AB
 # SPDX-License-Identifier: Apache-2.0
 
-choice
-	prompt "QEMU RISC-V VirtIO Board"
-	depends on SOC_SERIES_RISCV_VIRT
-
 config SOC_RISCV_VIRT
 	bool "QEMU RISC-V VirtIO Board"
 	select ATOMIC_OPERATIONS_BUILTIN
@@ -12,5 +8,6 @@ config SOC_RISCV_VIRT
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_C
-
-endchoice
+	select RISCV
+	select RISCV_PRIVILEGED
+	select RISCV_PRIVILEGED_STANDALONE