drivers: adc: stm32: add support for kernel source clock
Add support for ADC kernel source clock, similar to other STM32 drivers. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
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@ -159,7 +159,8 @@ struct adc_stm32_data {
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struct adc_stm32_cfg {
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struct adc_stm32_cfg {
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ADC_TypeDef *base;
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ADC_TypeDef *base;
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void (*irq_cfg_func)(void);
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void (*irq_cfg_func)(void);
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struct stm32_pclken pclken;
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const struct stm32_pclken *pclken;
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size_t pclk_len;
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uint32_t clk_prescaler;
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uint32_t clk_prescaler;
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const struct pinctrl_dev_config *pcfg;
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const struct pinctrl_dev_config *pcfg;
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const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME];
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const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME];
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@ -345,7 +346,7 @@ static void adc_stm32_calib_delay(const struct device *dev)
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uint32_t adc_rate, wait_cycles;
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uint32_t adc_rate, wait_cycles;
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if (clock_control_get_rate(clk,
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if (clock_control_get_rate(clk,
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(clock_control_subsys_t) &config->pclken, &adc_rate) < 0) {
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(clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) {
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LOG_ERR("ADC clock rate get error.");
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LOG_ERR("ADC clock rate get error.");
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}
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}
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@ -1217,13 +1218,36 @@ static int adc_stm32_channel_setup(const struct device *dev,
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return 0;
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return 0;
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}
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}
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/* This symbol takes the value 1 if one of the device instances */
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/* is configured in dts with a domain clock */
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0
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#endif
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static int adc_stm32_set_clock(const struct device *dev)
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static int adc_stm32_set_clock(const struct device *dev)
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{
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{
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const struct adc_stm32_cfg *config = dev->config;
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const struct adc_stm32_cfg *config = dev->config;
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
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ADC_TypeDef *adc = (ADC_TypeDef *)config->base;
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ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
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ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
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if (clock_control_on(clk,
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(clock_control_subsys_t) &config->pclken[0]) != 0) {
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return -EIO;
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}
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if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
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/* Enable ADC clock source */
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if (clock_control_configure(clk,
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(clock_control_subsys_t) &config->pclken[1],
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NULL) != 0) {
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return -EIO;
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}
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}
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X)
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LL_ADC_SetClock(adc, config->clk_prescaler);
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LL_ADC_SetClock(adc, config->clk_prescaler);
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#elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
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#elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
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@ -1276,11 +1300,6 @@ static int adc_stm32_init(const struct device *dev)
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*/
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*/
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data->acq_time_index = -1;
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data->acq_time_index = -1;
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if (clock_control_on(clk,
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(clock_control_subsys_t) &config->pclken) != 0) {
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return -EIO;
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}
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adc_stm32_set_clock(dev);
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adc_stm32_set_clock(dev);
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/* Configure dt provided device signals when available */
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/* Configure dt provided device signals when available */
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@ -1518,13 +1537,14 @@ PINCTRL_DT_INST_DEFINE(index); \
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\
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\
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ADC_STM32_IRQ_CONFIG(index) \
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ADC_STM32_IRQ_CONFIG(index) \
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\
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\
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static const struct stm32_pclken pclken_##index[] = \
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STM32_DT_INST_CLOCKS(index); \
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\
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static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
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static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
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.base = (ADC_TypeDef *)DT_INST_REG_ADDR(index), \
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.base = (ADC_TypeDef *)DT_INST_REG_ADDR(index), \
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ADC_STM32_IRQ_FUNC(index) \
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ADC_STM32_IRQ_FUNC(index) \
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.pclken = { \
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.pclken = pclken_##index, \
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.enr = DT_INST_CLOCKS_CELL(index, bits), \
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.pclk_len = DT_INST_NUM_CLOCKS(index), \
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.bus = DT_INST_CLOCKS_CELL(index, bus), \
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}, \
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.clk_prescaler = ADC_STM32_DT_PRESC(index), \
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.clk_prescaler = ADC_STM32_DT_PRESC(index), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
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.temp_channel = DT_INST_PROP_OR(index, temp_channel, 0xFF), \
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.temp_channel = DT_INST_PROP_OR(index, temp_channel, 0xFF), \
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