arch/x86/Kconfig: remove CONFIG_CMOV
The only we support cores that don't have CMOV insns are the MINUTEIAs, so we simply check for that rather this using a layer of indirection. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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@ -62,7 +62,6 @@ source "arch/x86/core/Kconfig"
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config CPU_ATOM
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# Hidden
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bool
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select CMOV
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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@ -80,7 +79,6 @@ config CPU_MINUTEIA
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config CPU_APOLLO_LAKE
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# Hidden
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bool
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select CMOV
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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@ -265,12 +263,6 @@ config REBOOT_RST_CNT
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endchoice
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config CMOV
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bool
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help
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This option signifies the use of an Intel CPU that supports
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the CMOV instruction.
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config CACHE_LINE_SIZE_DETECT
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bool "Detect cache line size at runtime"
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default y
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@ -47,15 +47,9 @@ static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
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__asm__ volatile (
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#if defined(CONFIG_CMOV)
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#ifdef CONFIG_CPU_MINUTEIA
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"bsfl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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: "cc"
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#else
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/* Minute IA doesn't support cmov */
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"bsfl %1, %0;\n\t"
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"jnz 1f;\n\t"
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@ -64,8 +58,15 @@ static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
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: "=r" (bitpos)
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: "rm" (op)
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: "cc"
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#else
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#endif /* CONFIG_CMOV */
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"bsfl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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: "cc"
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#endif /* CONFIG_CPU_MINUTEIA */
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);
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return (bitpos + 1);
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@ -97,14 +98,9 @@ static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
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__asm__ volatile (
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#if defined(CONFIG_CMOV)
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#ifdef CONFIG_CPU_MINUTEIA
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"bsrl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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#else
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/* again, Minute IA doesn't support cmov */
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"bsrl %1, %0;\n\t"
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"jnz 1f;\n\t"
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@ -114,7 +110,14 @@ static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
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: "rm" (op)
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: "cc"
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#endif /* CONFIG_CMOV */
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#else
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"bsrl %1, %0;\n\t"
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"cmovzl %2, %0;\n\t"
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: "=r" (bitpos)
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: "rm" (op), "r" (-1)
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#endif /* CONFIG_CPU_MINUTEIA */
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);
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return (bitpos + 1);
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