boards: add seeed studio LoRa-E5 Dev board

This commit adds support for the seeed studio LoRa-E5 Dev board,
which is powered by a module based on stm32wle5jc soc.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2021-05-01 20:10:17 +02:00 committed by Christopher Friedt
parent 15d8f1ea18
commit 808cc68e4c
10 changed files with 542 additions and 0 deletions

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# LoRa-E5 Dev board configuration
# Copyright (c) 2021 Thomas Stranger
# SPDX-License-Identifier: Apache-2.0
config BOARD_LORA_E5_DEV_BOARD
bool "LoRa E5 Development Board"
depends on SOC_STM32WLE5XX

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# LoRa-E5 Dev board configuration
# Copyright (c) 2021 Thomas Stranger
# SPDX-License-Identifier: Apache-2.0
if BOARD_LORA_E5_DEV_BOARD
config BOARD
default "lora_e5_dev_board"
endif # BOARD_LORA_E5_DEV_BOARD

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# SPDX-License-Identifier: Apache-2.0
board_runner_args(pyocd "--target=stm32wle5jcix")
board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load")
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)

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.. _lora_e5_dev_board:
Seeed Studio LoRa-E5 Dev Board
##############################
Overview
********
The LoRa-E5 Dev Board is a compact board for the evaluation of the
Seeed Studio LoRa-E5 STM32WLE5JC module.
The LoRa-E5-HF STM32WLE5JC Module supports multiple LPWAN protocols on the
868/915MHz frequency bands with up to 20.8dBm output power at 3.3V.
All GPIOs of the LoRa-E5 Module are laid out supporting
various data protocols and interfaces including RS-485 and Grove.
.. image:: img/lora_e5_dev_board.png
:width: 700px
:align: center
:alt: LoRa-E5 Dev board
Hardware
********
The boards LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
and a 32.768kHz crystal oscillator in a 28-pin SMD package.
This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
SX126X LoRa IP to support (G)FSK, BPSK, (G)MSK, and LoRa modulations.
- LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core
32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package
featuring:
- Ultra-low-power MCU
- RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
(G)FSK, (G)MSK, and BPSK modulations
- 256-Kbyte Flash memory and 64-Kbyte SRAM
- Hardware encryption AES256-bit and a True random number generator
- 1 user LED
- 1 user, 1 boot, and 1 reset push-button
- 32.768 kHz LSE crystal oscillator
- 32 MHz HSE oscillator
- 1 LM75A Temperature Sensor
- 1 SPI-Flash Bonding Pad(not populated)
- Board connectors:
- USB Type-C connector
- JST2.0 Battery connector (3-5V)
- 3 Grove connectors(2x IIC and 1x UART)
- RS-485 connector
- SMA-K and IPEX antenna connectors
- Delivered with SMA antenna (per default IPEX connector is disconnected)
- Flexible power-supply options: USB Type C, JST2.0, 2x AA 3V Battery Holder, or
external sources via header.
- Switchable 3.3V and 5V power rails.
- Comprehensive free software libraries and examples available with the
STM32CubeWL MCU Package
- Support of a wide choice of Integrated Development Environments (IDEs)
including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE
- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus,
and many other proprietary protocols
More information about the board can be found at the `LoRa-E5 Dev Board Wiki`_.
More information about LoRa-E5 STM32WLE5JC Module can be found here:
- `LoRa-E5 STM32WLE5JC Module Wiki`_
- `LoRa-E5 STM32WLE5JC Module datasheet`_
- `STM32WLE5JC datasheet`_
- `STM32WLE5JC reference manual`_
- `STM32WLE5JC on www.st.com`_
Supported Features
==================
The Zephyr LoRa-E5 Dev Board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | arm memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | rtc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig and dts files:
``boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig``
``boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts``
Connections and IOs
===================
LoRa-E5 Dev Board has 4 GPIO controllers. These controllers are responsible
for pin muxing, input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/lora_e5_dev_board_pinout.png
:align: center
:alt: LoRa-E5 Dev Board Pinout
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- LPUART_1 TX : PC1
- LPUART_1 RX : PC0
- USART_1 TX : PB6
- USART_1 RX : PB7
- USART_2 TX : PA2
- USART_2 RX : PA3
- I2C_2_SCL : PB15
- I2C_2_SDA : PA15
- SPI_2_NSS : PB9
- SPI_2_SCK : PB13
- SPI_2_MISO : PB14
- SPI_2_MOSI : PA10
- BOOT_PB : PB13
- USER_PB : PA0
- LED_1 : PB5
- ADC1 IN2 : PB3
Default Zephyr Peripheral to Connector Mapping:
-----------------------------------------------
.. rst-class:: rst-columns
- RS-485: USART_2
- grove_serial: USART_1
- grove_i2c: I2C_2
Power Rails
-----------
The board has multiple power rails, which are always turned on in the default
configuration.
+---------+-------------------+-------------------+
| Name | Derived from | Controlled by |
+=========+===================+===================+
| MAIN | battery, USB, ... | Always on |
+---------+-------------------+-------------------+
| VCC | MAIN | Always on |
+---------+-------------------+-------------------+
| 5V | MAIN | SOC pin PB10 |
+---------+-------------------+-------------------+
| 3V3 | VCC | SOC pin PA9 |
+---------+-------------------+-------------------+
A list of the devices and their power rails:
+--------------------+---------+
| Device | Rail |
+====================+=========+
| STM32WLE5JC | VCC |
+--------------------+---------+
| RS-485 Transceiver | 3V3 |
+--------------------+---------+
System Clock
------------
LoRa-E5 Development board System Clock could be driven by the low-power
internal(MSI), High-speed internal(HSI) or High-speed external(HSE) oscillator,
as well as main PLL clock.
By default System clock is driven by the MSI clock at 48MHz.
Programming and Debugging
*************************
Applications for the ``lora_e5_dev_board`` board configuration can be built the
usual way (see :ref:`build_an_application`).
In the factory the module is flashed with an DFU bootloader, an AT command
firmware, and the read protection level 1 is enabled.
So before you can program a zephyr application to the module for the first time
you have to reset the read protection to level 0.
In case you use an st-link debugger you can use the STM32CubeProgrammer GUI to
set the RDP option byte to ``AA``,
or use the STM32_Programmer_CLI passing the ``--readunprotect`` command
to perform this read protection regression.
The RDP level 1 to RDP level 0 regression will erase the factory programmed AT
firmware, from which seeed has neither released the source code nor a binary.
Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible,
so the system bootloader will only be executed if configured in the option bytes.
Flashing
========
The LoRa-E5 Dev Board does not include a on-board debug probe.
But the module can be debugged by connecting an external debug probe to the
blue 2.54mm header labeled ``SWIM/SWD``.
Depending on the external probe used, ``openocd``, the ``stm32cubeprogrammer``,
``pyocd``, ``blackmagic``, or ``jlink`` runner can be used to flash the board.
Additional notes:
- Pyocd: For STM32WL support Pyocd needs additional target information, which
can be installed by adding "pack" support with the following pyocd command:
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32wl
Flashing an application to LoRa-E5 Dev board
--------------------------------------------
Connect the LoRa-E5 to your host computer using the external debug probe.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your board:
Per default the console on ``usart1`` is available on the USB Type C connector
via the build-in USB to UART converter.
.. code-block:: console
$ picocom --baud 115200 /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: lora_e5_dev_board
:goals: build flash
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`blinky-sample` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: lora_e5_dev_board
:maybe-skip-config:
:goals: debug
.. _LoRa-E5 Dev Board Wiki:
https://wiki.seeedstudio.com/LoRa_E5_Dev_Board/
.. _LoRa-E5 STM32WLE5JC Module Wiki:
https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/
.. _LoRa-E5 STM32WLE5JC Module datasheet:
https://files.seeedstudio.com/products/317990687/res/LoRa-E5%20module%20datasheet_V1.0.pdf
.. _STM32WLE5JC on www.st.com:
https://www.st.com/en/microcontrollers-microprocessors/stm32wle5jc.html
.. _STM32WLE5JC datasheet:
https://www.st.com/resource/en/datasheet/stm32wle5jc.pdf
.. _STM32WLE5JC reference manual:
https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf

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/*
* Copyright (c) 2021 Thomas Stranger
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <seeed/lora-e5.dtsi>
/ {
model = "Seeed Studio LoRa-E5 Dev Board";
compatible = "seeed,lora-e5-dev-board";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &flash0;
};
leds {
compatible = "gpio-leds";
red_led_1: led_0 {
gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
label = "User LED1";
/* the led can be disconnected, using J16 (D5) */
};
};
gpio_keys {
compatible = "gpio-keys";
boot_button: button_0 {
label = "SW1";
gpios = <&gpiob 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
user_button: button_1 {
label = "SW2";
gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
/* user_button can be disconnected, using J14 (D0) */
};
};
aliases {
led0 = &red_led_1;
sw0 = &boot_button;
sw1 = &user_button;
};
pwr_3v3: pwr-3v3-ctrl {
/*
* PWR rail for SPI-flash, Temp-Sensor, RS-485 Transceiver,
* and for external devices(Grove, header).
* Requires closed J15 (D9)
*/
compatible = "regulator-fixed-sync", "regulator-fixed";
label = "pwr-3v3-ctrl";
regulator-name = "pwr-3v3-ctrl";
enable-gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
status = "okay";
};
pwr_5v: pwr-5v-ctrl {
/*
* Available for external devices on header J2
* Requires closed J6 (D10)
*/
compatible = "regulator-fixed-sync", "regulator-fixed";
label = "pwr-5v-ctrl";
regulator-name = "pwr-5v-ctrl";
enable-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
status = "okay";
};
};
&clk_msi {
status = "okay";
msi-range = <11>;
};
&pll {
clocks = <&clk_msi>;
div-m = <3>;
mul-n = <6>;
div-r = <2>;
div-q = <2>;
div-p = <2>;
status = "okay";
};
&rcc {
clocks = <&clk_msi>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
ahb3-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pc1 &lpuart1_rx_pc0>;
current-speed = <115200>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
current-speed = <115200>;
status = "okay";
/* PB4 can select RS-485 TX, when J17 (A4) is closed */
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb15 &i2c2_sda_pa15>;
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
/* LM75ADP temperature sensor on addr 0x48 */
};
/* Attention!: the spi-sck pin is in confict with the boot_button on pb13 */
&spi2 {
pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pa10>;
status = "okay";
/* unpopulated footprint for spi flash */
};
&rtc {
status = "okay";
};
&iwdg {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc_in2_pb3>;
status = "okay";
};
/* connectors: */
grove_serial: &usart1 {};
grove_i2c: &i2c2 {};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* 16KB (8x2kB pages) of storage at the end of the flash */
storage_partition: partition@3c000 {
label = "storage";
reg = <0x0003c000 0x00004000>;
};
};
};
/*
* Other Pins:
* Not assigned: None
* Debug: PA13(swdio), PA14(swclk)
*/

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identifier: lora_e5_dev_board
name: Seeedstudio LoRa-E5 Dev Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- nvs
- spi
- uart
- watchdog

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CONFIG_SOC_SERIES_STM32WLX=y
CONFIG_SOC_STM32WLE5XX=y
# enable uart driver
CONFIG_SERIAL=y
# enable pinmux
CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable regulator for the power-rails
CONFIG_REGULATOR=y

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source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32wlx.cfg]
reset_config srst_only